3.4 Design Verification
A detailed Failure Mode, Effects, and Diagnostics Analysis (FMEDA) report is available from
Flowserve. This report details all failure rates and failure modes.
The achieved Safety Integrity Level (SIL) of an entire Safety Instrumented Function (SIF) design must
be verified by the designer via a calculation of PFDavg considering architecture, proof test interval,
proof test effectiveness, any automatic diagnostics, average repair time and the specific failure rates
of all products included in the SIF. Each subsystem must be checked to assure compliance with
minimum hardware fault tolerance (HFT) requirements. The exida exSILentia
®
tool is recommended
for this purpose as it contains accurate models for the Mark Series valve and its failure rates.
When using a Mark Series valve in a redundant configuration, a common cause factor of 5% should
be included in safety integrity calculations.
The failure rate data listed the FMEDA report is only valid for the useful life time of a Mark Series
valve. The failure rates will increase sometime after this time period. Reliability calculations based on
the data listed in the FMEDA report for mission times beyond the lifetime may yield results that are
too optimistic, i.e. the calculated Safety Integrity Level will not be achieved.
3.5 SIL Capability
3.5.1 Systematic Integrity
The product has met manufacturer design process requirements of Safety Integrity Level (SIL) 3.
These are intended to achieve sufficient integrity against systematic errors of design by the
manufacturer. A Safety Instrumented Function (SIF) designed with this product must not be used at
a SIL level higher than the statement without “prior use” justification by end user or diverse
technology redundancy in the design.
3.5.2 Random Integrity
The Mark Series valve is a Type A Device. Therefore based on the SFF between 60% and 90%,
when the Mark Series valve is used as the only component in a final element subassembly, a design
can meet SIL 2 @ HFT=0.
When the final element assembly consists of many components (Mark Series valve, solenoid, quick
exhaust valve, etc.) the SIL must be verified for the entire assembly using failure rates from all
components. This analysis must account for any hardware fault tolerance and architecture
constraints.
3.5.3 Safety Parameters
For detailed failure rate information refer to the Failure Modes, Effects and Diagnostic Analysis
Report for the Mark Series valve.
3.6 Connection of the Mark Series valve to the SIS Logic-solver
The Mark Series valve is connected to the safety rated logic solver which is actively performing the
safety function as well as automatic diagnostics designed to diagnose potentially dangerous failures
within the Mark Series valve, (i.e. partial valve stroke test).
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