Fluke 41B - Page 31

Theory of Operation
Circuit Descriptions
2
2-11
RD*
DSPCLOCK
WR*
A4
A5
A14
A15
XY
DS*
PS*
CHL
ATOD_EESER
FS0
CS_AD
SCK
DOUT_AMPS
CS_SRAM*
CS_BOOTROM*
CS_EEPROM*
CS_GAIN*
CS_EEPOT*
INC_EEPOT*
CS_LCD*
RD*
R3
R2
R1
R0
IRQA*
DOUT
DOUT_VOLTS
DOUT_EESER
CHL
ATOD_EESER
CS_EESER
MEMORY
DECODE
AND
EEPOT
INTERFACE
LCD
INTERFACE
SERIAL
MUX
KEYPAD INTERRUPTS
SHIFT
REGISTER
RA13
t2f.eps
Figure 2-2. PLD Block Diagram
2-29. Memory Decoding
The signals A15, A14, A5, A4, PS*, DS*, XY, and WR* are used to map out the SRAM,
EPROM, EEPROM, Gain Latch, EEPOT, and LCD in program and data space. Although
the SRAM looks like one contiguous RAM space, it’s actually divided into three
separate memory spaces. Table 2-3 shows where external memory and I/O are mapped.
Table 2-3. Memory Map
Device X Data Space Y Data Space Program Space
SRAM (U7-5) $8000 - $9FFF $8000 - $9FFF $0000 - $1FFF
$4000 - $5FFF
EPROM (U4) $8000 - $FFFF
EEROM (U3) $4000 - $7FFF
LCD $FFC0 - $FFC1
LATCH (U1) $FFD0
EEPOT (U8) $FFE0, $FFF0