The MB 91F467 / MB 86276 Evaluation Board is a comprehensive development and evaluation platform designed for system architects, hardware, and software developers. This manual provides detailed technical information, covering system architecture, hardware architecture, and mechanical specifications. It serves as an engineer's reference for evaluation, system development, and prototyping based on the module, encompassing all available hardware versions, configurations, and revision states.
Function Description:
The evaluation board is populated with a 32-bit CPU, the MB91F467, and a graphic display controller, the MB 86276, also known as LIME. It integrates various memory components, including Flash memory, SDRAM, and SRAM, along with a wide range of interfaces to support diverse applications.
Important Technical Specifications:
CPU (MB91F467DA):
The CPU MB91F467DA from Fujitsu (U500) is a 32-bit processor with a core frequency of 96 MHz and a resource frequency of 48 MHz. It includes a watchdog timer, bit search function, and reset input. The clock modulator manages clock signals.
Memory:
- Flash external: 1024 kB + 64 kB
- D-bus RAM: 32 KB
- GP RAM: 32 kB
- Direct mapped cache: 8 kB
- Boot-ROM: 4 kB
Peripherals:
- RTC: 1 channel
- Free Running Timer: 8 channels
- ICU: 8 channels
- OCU: 8 channels
- Reload Timer: 8 channels
- PPG: 12 channels
- PFM: 1 channel
- Sound Generator: 1 channel
- UpDown Counter: 3 channels
- C_CAN: 3 channels (32 msg buffer)
- LIN-USART: 5 channels (4 channels FIFO)
- I2C: 3 channels
- FR external bus: 32-bit address / 32-bit data 26-bit address / 32-bit data
- External Interrupts: 14 channels
- SMC: 6 channels
- ADC: 24 channels (10-bit)
- Alarm Comparator: 1 channel
- Low voltage detection
- Clock Supervisor
The CPU is connected to external memory, including 2x 1 Gbit Flash Memory (U580, U581), 2x 128Mx16 SDRAM (U590, U591), and 512kx16 SRAM (U592). The mode pins of the CPU (MD_2 and MD_1) are fixed to logical '0'. The logical level of mode pin MD_0 can be set via switch SW500: open for logical '1' and closed for logical '0'.
- MD[2:0] = '000': Internal ROM Vector mode, Reset vector access: internal Flash (standard setting).
- MD[2:0] = '001': External ROM Vector mode, Reset vector access: external.
Graphic Display Controller (MB86276 LIME):
The graphic display controller MB86276 (U300), also known as LIME, is connected to the CPU.
Features:
- CMOS 0.18µm technology
- Internal and memory frequency: 133MHz (generated by on-chip PLL)
- Base-clock for display clocks: 400.9MHz (generated by on-chip PLL)
- Display resolutions: typically from 320x240 up to 1280x768
- 6 layers of overlay display (windows)
- Alpha Plane and constant alpha value for each layer
- Digital Video input: various formats including YUV, RGB
- Video Scaler: up/down scaling
- Brightness, Contrast, Saturation control for video input
- RGB digital output: 8bit x 3
- Built-in alpha blending, anti-aliasing, and chroma-keying
- Rendering Engine for various kinds of 2D graphic acceleration functions
- Texture Mapping Unit for 2D polygon support up to 4096x4096 textures
- Bit-Blt Unit for transfers up to 4096x4096 areas
- Alpha Bit-Blt and ROP2 functions
- External 32-bit SDRAM interface for up to 32MB graphic memory
- Parallel host interface: (FR, SH3, SH4, V850, SparcLite etc)
- New additional serial control interface as host interface: (I2C based)
- Internal and external DMA support
- I2C interface and GPIO inputs/outputs
- Supply voltage: 3.3V (I/O), 1.8V (Internal)
- BGA-256 Package: (1.27mm pitch)
- Typical power consumption: < 1.0 W (estimated)
- Temperature range: -40..+85 °C
Interfaces:
- Power Supply: Connects to a DC power supply between 5 and 34 V DC, requiring approximately 10 Watts at connector X100. Polarity must be observed. Protection against wrong polarity (D109) and overcurrent (F100) is implemented. The LT3481 (U101) regulates +5 V from the input, and the LT1940EFE-PBF (U100) regulates +3.3 V and +1.8 V from the +5 V supply.
- Serial Ports: Two 9-pin Sub-D female connectors (X800 for UART 0, X801 for UART 1) provide RS-232 inputs and outputs. MAX3243EIPW transceivers (U800, U801) with enhanced ESD protection are used.
- Pin assignments for X800 (X801 is identical, changing index 0 to 1):
- Pin 1: RS232_0_CD (Data carrier detect)
- Pin 2: RS232_0_TXD (Transmit data)
- Pin 3: RS232_0_RXD (Receive data)
- Pin 4: RS232_0_DSR (Data set ready)
- Pin 5: GND (Ground)
- Pin 6: RS232_0_DTR (Data terminal ready)
- Pin 7: RS232_0_CTS (Clear to send)
- Pin 8: RS232_0_RTS (Request to send)
- Pin 9: RS232_0_RI (Ring indicator)
- Ethernet: An RJ45 connector (X600) provides a 10/100 Ethernet interface, implemented with the LAN9218 controller (U600) from SMSC, connected to the CPU's 32-Bit processor interface. The LAN9218 is IEEE 802.3 10BASE-T and 802.3u 100BASE-TX compliant, supporting HP Auto-MDIX. It includes an integrated Ethernet MAC and PHY, large transmit and receive data FIFOs, and 16-kByte internal SRAM.
- Default setting: 100 Mbps, half-duplex, auto-negotiation enabled (SPD_SEL pin strapped to VCC via R609).
- Configurable: 10 Mbps, half-duplex, auto-negotiation disabled (SPD_SEL pin strapped to ground via 0 Ohm resistor R612).
- FIFO_SEL pin of U600 can be strapped to ground by 0 Ohm resistor R613. If not populated, it's strapped to VCC via R610, directing all accesses to RX or TX data FIFO and ignoring upper addresses A[7:3].
- Auto-MDIX is enabled by default (AMDIX_EN pin strapped to VCC via R611). It can be disabled by strapping to ground via 0 Ohm resistor R614.
- CAN Interfaces: Two CAN interfaces (CAN0 and CAN1) are available at the 9-pin SubD female connector X700. The SN65HVD234D transceivers (U700 and U701) from Texas Instruments provide transmit and receive capability.
- RS pin 8 of SN65HVD234 offers three modes: high-speed (pin 8 to ground), slope control (resistor to ground), or low-power standby (high logic level to pin 8).
- Ultralow-current sleep mode is entered when a low logic level is applied to EN pin 5.
- 120 Ohm termination is configurable per line via switches: SW700 for CAN 0, SW701 for CAN 1.
- Pin assignments for X700:
- Pin 1: VCC33 (3.3V switchable via R702)
- Pin 2: EXT_CAN0L (CAN 0 Low)
- Pin 3: GND (Ground)
- Pin 4: EXT_CAN1L (CAN 1 Low)
- Pin 5: GND (Ground)
- Pin 6: GND (Ground)
- Pin 7: EXT_CAN0H (CAN 0 High)
- Pin 8: EXT_CAN1H (CAN 1 High)
- Pin 9: VCC50 (5V switchable via R701)
- Video Inputs:
- Cinch video connectors X480 (AVIN0) and X481 (AVIN1) are connected directly to GDC module interface connector X301 (pins 35, 37, and ground pins 33, 34).
- Cinch connector X500 for CVBS and FTSH-106-01-DV connector X501 for digital video inputs (ITU 656 format).
- Analog input signals are decoded to digital video signals (ITU 656 format) by the SAA7113H 9-bit video input processor (U500) from Philips Semiconductors.
- Outputs from SAA7113H are connected to video capture interface 0 from JADE.
- SAA7113H is controlled by I2C interface 0. RTS0 pin is strapped to ground, setting slave address for readings to 0x49 and for writings to 0x48.
- Video Outputs:
- Digital RGB video output 0 from LIME is connected to connector X402, Sil164CT64 transmitter (U400), and ADV7125JSTZ240 triple 8-Bit high-speed video DAC (U402).
- Digital RGB video output 1 from LIME is connected to connector X403, Sil164CT64 transmitter (U401), and ADV7125JSTZ240 triple 8-Bit high-speed video DAC (U403).
- Connectors X402 and X403 are FTSH-120-01-L-DV-EJ-P from Samtec.
- Sil164CT64 (U400 and U401) from Silicon Image uses PanelLink® Digital technology, supporting displays from VGA to UXGA resolutions (25 – 165 Mpps).
- Link interface of U400 connects to DVI-I connector X400. Link interface of U401 connects to DVI connector X401.
- Sil164 supports 12-bit mode (1½ pixel per clock edge) or 24-bit mode (1-pixel / clock input for true color). In 24-bit mode, it supports single or dual edge clocking. In 12-bit mode, it supports dual edge single clocking or single edge dual clocking.
- Sil164 is programmable via I2C interface. Multi-function address inputs A1, A2, A3 of U400 are strapped to ground (R409, R410, R412), setting slave address for readings to 0x71 and for writings to 0x70. Multi-function address inputs A2, A3 of U401 are strapped to ground (R423, R424) and A1 is strapped to VCC (RN402), setting slave address for readings to 0x73 and for writings to 0x72.
- Sil164 supports receiver and hot plug detection.
- ADV7125JSTZ240 (U402 and U403) from Analog Devices convert digital RGB666 video output signals from LIME to analog video signals. Outputs from U402 connect to DVI-I connector X400, and outputs from U403 connect to DVI-I connector X401.
- Pin assignments for X402 (X403 is identical, changing index 0 to 1):
- Pin 1, 2: GND (Ground)
- Pin 3-10: VO0_B0-B7 (Digital RGB output 0-7 Data blue)
- Pin 11-18: VO0_G0-G7 (Digital RGB output 0-7 Data green)
- Pin 19-22: VCC33 (+3.3 V)
- Pin 23-30: VO0_R0-R7 (Digital RGB output 0-7 Data red)
- Pin 31: VO0_HSYNC (Video output interface horizontal sync output)
- Pin 32: VO0_VSYNC (Video output interface vertical sync output)
- Pin 33: VO0_DE (DE / CSYNC)
- Pin 34: VO0_CSYNC (DE / CSYNC)
- Pin 35: VO0_GV
- Pin 36: VO0_CLK_RGBD (Video output interface dot clock output)
- Pin 37: I2C_SCL (I2C interface 0 SCL)
- Pin 38: I2C_SDA (I2C interface 0 SDA)
- Pin 39, 40: GND (Ground)
- GPIOs: Some GPIOs from the CPU are available at connector X900 FTSH-110-01-L-DV-K-A-P from Samtec.
- Pin assignments for X900:
- Pin 1: VCC33 (+3.3 V)
- Pin 2-7: GPIO0-5 (P14_0, P14_1, P16_4, P16_5, P16_6, P16_7)
- Pin 8-13: GPIO6-11 (P27_0, P27_1, P27_2, P27_3, P27_4, P27_5)
- Pin 14-19: GPIO12-17 (P27_6, P27_7, P26_0, P26_1, P26_2, P26_3)
- Pin 20: GND (Ground)
Usage Features:
- Buttons:
- SW100 (unlabeled): Generates a reset.
- SW501 (labeled ABORT): Generates interrupt 0 (P24_0).
- SW502 (labeled TEST1): Generates interrupt 4 (P24_4).
- SW503 (labeled TEST2): Generates interrupt 5 (P24_5).
- SW504 (labeled TEST3): Generates interrupt 6 (P24_6).
- LEDs:
- D104 (labeled RES): On when reset is active.
- D105 (labeled 1.8V): On when 1.8 V power supply is active.
- D106 (labeled 3.3V): On when 3.3 V power supply is active.
- D107 (labeled 5.0V): On when 5.0 V power supply is active.
- D500 (DIAG1), D501 (DIAG2), D502 (DIAG3), D503 (DIAG4): Free usable LEDs. A logical '0' port signal switches the LED on, and a logical '1' port signal switches it off.
- LED GPIO assignment:
- D500: DIAG1, P25_0
- D501: DIAG2, P25_1
- D502: DIAG3, P25_2
- D503: DIAG4, P25_3
Maintenance Features:
- Reset Circuit: The TPS3307-33DGN triple processor supervisor (U102) from Texas Instruments generates a power-on reset and monitors the 1.8 V, 3.3 V, and 5.0 V power supplies. A reset is also generated when the SW100 button is pressed.
- Power Supply Protection: D109 protects against wrong polarity, and F100 protects against overcurrent. However, excessive current can still damage the power supply or generate significant heat.
- Hardware Variants: Currently, only PCB version PA6 is available without variants.
- Mechanical Dimensions: The board measures 160.0 x 100.0 mm.
This manual is a critical resource for anyone working with the MB 91F467 / MB 86276 Evaluation Board, providing the necessary information to understand, operate, and develop solutions using this platform.
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