5AX
4-14
4.7. CHIPSET FEATURES SETUP
Figure 4.4: Chipset Features Setup
• Auto Configuration
The default value is Enabled.
Enabled For General State.
Disabled For Special SDRAM Timing and ISA CLK.
• Host Read DRAM Command Mode.
The default value is Syn.
Bypass Set DRAM Cycle Start at T3 clock after ADS#.
Syn. Set DRAM Cycle Start at T3+1 clock after ADS#.
• AT Bus Clock
The default value is CLK2/4.
CLK2/3 Set AT Bus Clock to CLK2/3.
CLK2/4 Set AT Bus Clock to CLK2/4.
7.159MHz Set AT Bus Clock to 7.159MHz.