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Details the Arm® Cortex®-M23 processor, covering its architecture, energy efficiency, instruction set, and integration with the Nested Vectored Interrupt Controller (NVIC).
Describes the system architecture of GD32E23x series, based on AMBA 5 AHB-LITE, including masters (Cortex®-M23 core, DMA) and slaves (flash, SRAM, AHB1, AHB2).
Details the memory organization of the GD32E23x series, covering program memory, data memory, registers, and I/O ports within the 4-GB address space.
Explains the three types of boot sources selectable via option bytes and BOOT0 pins, detailing the boot modes: Main Flash, System Memory, and On-chip SRAM.
Describes the SYSCFG registers, including SYSCFG_CFG0 for peripheral remapping and boot mode selection, and EXTI source selection registers.
Covers the device electronic signature, containing memory density information and the unique 96-bit device ID stored in the Flash memory's information block.
Provides an overview of the Flash Memory Controller (FMC), detailing its functions for on-chip flash memory, including page erase, mass erase, and programming capabilities.
Lists the characteristics of the FMC for GD32E23x series, including flash memory size, waiting time, pre-fetch buffer, and page erase/program protection.
Explains the core functionalities provided by the Flash Memory Controller (FMC), including page erase, mass erase, and word/double word programming.
Provides detailed descriptions of the FMC registers, including wait state, unlock key, option byte unlock key, and status registers.
Discusses power consumption as a key issue for GD32E23x series devices, detailing power saving modes and power domains.
Lists the characteristics of the PMU, including power domains, power saving modes, internal voltage regulator, and low voltage detector.
Details the internal configuration of the PMU and its relevant power domains, including Sleep, Deep-sleep, and Standby modes.
Describes the control and status registers for the Power Management Unit (PMU), such as PMU_CTL and PMU_CS.
Covers the three types of reset control: power reset, system reset, and backup domain reset, detailing their triggers and effects.
Explains the clock control unit's functions, including oscillators, prescalers, and clock multiplexers for generating system clocks.
Defines the registers associated with the Reset and Clock Unit (RCU), such as control and configuration registers.
Introduces the Nested Vectored Interrupt Controller (NVIC) and the EXTI controller, highlighting their roles in exception and interrupt handling.
Lists the characteristics of the EXTI controller, including system exception, maskable peripheral interrupts, and trigger types.
Describes how the NVIC and EXTI cooperate to prioritize and handle exceptions and interrupts, including state saving and tail-chaining.
Details the EXTI's role in generating interrupts and events, supporting up to 21 independent edge detectors with configurable trigger types.
Defines the registers for the EXTI module, including interrupt enable, event enable, trigger enable, and pending registers.
Describes the general-purpose I/O pins (GPIO) and their alternate functions (AF), covering pin sharing and configuration for specific applications.
Lists the characteristics of GPIO pins, including input/output direction control, Schmitt trigger, pull-up/down, output modes, and speed selection.
Explains how GPIO ports can be configured as inputs, outputs, AF functions, or analog mode with customizable pull-up/pull-down resistors.
Defines the registers for GPIO configuration, including port control, output mode, output speed, and pull-up/down registers.
Introduces the Cyclic Redundancy Check (CRC) as an error-detecting code used in digital networks and storage devices.
Lists the characteristics of the CRC management unit, supporting various data sizes, configurable polynomials, and initial values.
Describes the CRC calculation unit's capabilities, supporting various data sizes and user-configurable polynomials and initial values.
Details the CRC registers, including data, free data, control, initialization data, and polynomial registers.
Explains the Direct Memory Access (DMA) controller, a hardware method for transferring data between peripherals and memory without CPU intervention.
Lists DMA characteristics, including programmable data length, configurable channels, AHB/APB peripheral access, and priority levels.
Explains DMA operations, including data transfer, source/destination addresses, transfer count, and channel configurations.
Defines the DMA registers, such as interrupt flag, interrupt flag clear, channel control, counter, and base address registers.
Introduces the debug, trace, and test features of the GD32E23x series, implemented with Arm CoreSight™ module and daisy chained TAP controller.
Covers the Serial Wire Debug (SWD) interface, including pin assignments and debug capabilities accessible via a debug tool.
Explains the DBG hold unit's role in debugging power saving modes and specific peripherals like TIMER, I2C, RTC, WWDGT, and FWDGT.
Defines the registers for the Debug module, including ID code and control registers for halt states and peripheral debugging.
Introduces the 12-bit successive approximation ADC module, detailing its sampling capabilities, conversion results storage, and oversampling scheme.
Lists ADC characteristics, including resolution, calibration, sampling time, data storage modes, DMA support, and analog input channels.
Details the ADC's internal input signals and pin definitions, including temperature sensor and reference voltage channels.
Describes the ADC's operation modes such as single, continuous, discontinuous, and scan modes, along with calibration and interrupt generation.
Defines the ADC registers, including status, control, sample time, watchdog threshold, and routine sequence registers.
Introduces the general-purpose comparator (CMP) that can work standalone or with timers.
Lists the main features of the comparators, including rail-to-rail operation, hysteresis, speed, and analog input sources.
Explains the CMP's functionality, including clock and reset, I/O configuration, operating modes, and hysteresis.
Details the CMP registers, focusing on the control/status register (CMP_CS) for configuring and monitoring comparator behavior.
Describes the FWDGT, its characteristics such as a 12-bit down counter, and its function overview including prescaler and reload registers.
Explains the WWDGT, its characteristics like a 7-bit down counter, and its function overview, including reset conditions and early wakeup interrupts.
Provides an overview of the RTC, covering time and date formats, daylight saving time, power saving modes, and calendar accuracy improvements.
Lists RTC characteristics, including daylight saving compensation, external clock usage, atomic clock adjustment, sub-second adjustment, and tamper sources.
Covers the RTC's functional overview, including block diagram, clock sources, prescalers, shadow registers, and alarm functions.
Defines the RTC registers, such as time, date, control, status, prescaler, alarm, and backup registers.
Details the advanced timer (TIMER0), its characteristics, block diagram, function overview, and register definitions.
Describes the general level0 timer (TIMER2), covering its overview, characteristics, block diagram, function overview, and register definitions.
Explains the general level2 timer (TIMER13), including its overview, characteristics, block diagram, and function overview.
Introduces the basic timer module (TIMER5), a 16-bit counter for unsigned counting, configurable for DMA request generation.
Lists characteristics of the basic timer, including counter width, clock source, counter modes, prescaler, and auto-reload function.
Provides a block diagram detailing the internal configuration of the basic timer module.
Explains the basic timer's function overview, covering clock source configuration and clock prescaler.
Introduces the Infrared Ray Port (IFRP) module, used for controlling infrared LEDs and sending infrared data for remote control applications.
Lists the characteristics of the IFRP output signal, influenced by TIMER15 and TIMER16 configurations.
Explains how IFRP integrates outputs from TIMER15 and TIMER16 to generate infrared ray signals, including GPIO configuration and high current output.
Provides an overview of the Universal Synchronous/Asynchronous Receiver/Transmitter (USART) and its flexible serial data exchange interface.
Lists the key characteristics of the USART, including NRZ format, full/half-duplex, FIFO, and programmable baud-rate generator.
Details the USART's function overview, including frame format, baud rate generation, transmitter, receiver, and DMA usage.
Defines the USART registers, covering control registers, status registers, and configuration registers for various modes.
Introduces the I2C module as an industry-standard serial interface for MCU communication with external I2C devices.
Lists I2C characteristics like parallel-bus to I2C-bus conversion, master/slave support, addressing modes, and clock speeds.
Explains the I2C function overview, including SDA/SCL lines, START/STOP signals, clock synchronization, arbitration, and communication flow.
Defines the I2C registers, including control registers, slave address registers, transfer buffer, and status registers.
Introduces the SPI/I2S module for communication with external devices using SPI or I2S protocols, supporting various modes and standards.
Lists characteristics for SPI (master/slave, duplex modes, FIFO, frame size) and I2S (standards, data length, clock).
Details SPI function overview, including block diagram, signal description, clock timing, data format, FIFO, NSS function, operation modes, DMA, and interrupts.
Explains the I2S function overview, including block diagram, signal description, audio standards, operation modes, and initialization sequence.
Defines the SPI and I2S registers, covering control registers, status registers, and CRC/FIFO configuration.
Provides an overview of the OPA modules, highlighting their low noise, low voltage, and low power characteristics.
Lists the characteristics of the OPA, including offset voltage, gain, bandwidth, supply voltage, and power consumption.
Explains the OPA's function overview, covering enablement, combinatorial work with ADC, and usage with SW functions.
Provides a list of abbreviations used for registers, explaining their read/write access and clearing methods.
Defines common terms used in the document, such as Word, Half-word, Byte, IAP, ICP, Option bytes, AHB, APB, RAZ, WI, and RAZ/WI.
Refers to the device datasheet for information on peripheral availability and number across different MCU series types.
General| Core | ARM Cortex-M23 |
|---|---|
| Operating Frequency | Up to 72 MHz |
| GPIO Pins | Up to 51 |
| Temperature Range | -40°C to +85°C |
| ADC | 12-bit |
| Timers | Up to 6 |
| Communication Interfaces | I2C, SPI, USART |
| Package | LQFP48, LQFP64 |
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