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Overview of the 32-bit processor with low interrupt latency and debug features.
Describes the AHB matrix, masters, slaves, and bus connections.
Organizes memory into linear 4-Gbyte address space with pre-defined regions.
Explains boot sources selected via option byte and BOOT0 pin.
Covers system configuration registers, including base address and specific register details.
Provides memory density information and unique device ID.
Describes the FMC functions for on-chip flash memory, including page erase and programming.
Lists key features of the flash memory, including size, page size, and protection.
Explains the overall functionality and architecture of the flash memory.
Describes protection against illegal code/data access with three levels.
Defines FMC registers, including their base address and offsets.
Introduces PMU functions for power saving modes (Sleep, Deep-sleep, Standby).
Lists PMU features like power domains, saving modes, LDO, LVD, and battery power support.
Explains PMU internal configuration and relevant power domains.
Defines PMU registers, including base address and offsets.
Covers control of power reset, system reset, and backup domain reset.
Describes clock sources, prescalers, multiplexers, and clock gating.
Defines RCU registers, including base addresses and offsets.
Introduces the CTC for automatic trimming of the internal 48MHz RC oscillator.
Lists CTC features like reference signal sources, automatic trimming, and flags.
Explains the CTC's operation, including reference signal generation and trim counter.
Defines CTC registers, including base address and offsets.
Introduces NVIC and EXTI for exception and interrupt processing.
Lists EXTI features like edge detectors, trigger types, and interrupt sources.
Explains how Cortex-M4 processor and NVIC handle exceptions and interrupts.
Shows the block diagram of the EXTI module, including edge detection and trigger logic.
Details EXTI capabilities for generating interrupts/events from GPIO and internal modules.
Defines EXTI registers, including base address and offsets.
Introduces GPIO pins and their configurable registers for various applications.
Lists GPIO features like direction control, pull-up/down, speed, alternate functions.
Explains GPIO configuration modes: input, output, alternate function, and analog.
Defines GPIO registers, including base addresses for different ports.
Introduces CRC as an error-detecting code for data integrity.
Lists CRC features like data size support, reversal, polynomial configuration.
Explains CRC calculation, free register, reversible functions, and initial value configuration.
Defines CRC registers, including base addresses and offsets.
Introduces DMA for efficient data transfer between peripherals and memory without CPU intervention.
Lists DMA features like programmable length, channels, priority, and transfer modes.
Shows the internal configuration of the DMA controller, including arbiter and channels.
Explains DMA operation, peripheral handshake, and arbitration.
Defines DMA registers, including base addresses and offsets.
Introduces debug and trace features, including SWD and trace functions.
Describes the SWD interface and its pin assignment.
Explains debug support for power saving modes and peripherals.
Defines DBG registers, including base addresses and offsets.
Introduces the 12-bit ADC for sampling analog signals from external and internal channels.
Lists ADC features like resolution, calibration, sampling time, data storage, and DMA support.
Provides details on ADC module block diagram, internal signals, and pin definitions.
Explains ADC module block diagram, foreground calibration, dual clock domains, and ADCON enable.
Defines ADC registers, including base addresses and offsets.
Introduces DAC for converting 12-bit digital data to voltage on external pins.
Lists DAC features like resolution, alignment, DMA support, triggers, buffer, and noise wave.
Explains DAC enable, output buffer, data configuration, trigger sources, and DMA function.
Defines DAC registers, including base addresses and offsets.
Introduces general purpose comparators CMP0 and CMP1.
Lists comparator features like rail-to-rail, hysteresis, speed, analog input sources.
Explains CMP clock and reset, I/O configuration, operating modes, and hysteresis.
Defines CMP registers, including base address and offsets.
Introduces FWDGT, its clock source (IRC40K), and reset behavior.
Introduces WWDGT for detecting system failures and its reset conditions.
Defines FWDGT registers, including control, prescaler, and reload registers.
Introduces RTC for timekeeping, calendar functions, and power saving modes.
Lists RTC features like daylight saving, atomic clock adjustment, tamper detection, and backup registers.
Explains RTC block diagram, clock sources, prescalers, shadow registers, and alarm functions.
Defines RTC registers, including base addresses and offsets.
Introduces advanced timer module TIMER0 with four channels for capture, compare, and PWM.
Introduces general level0 timers TIMER1 and TIMER2 with four channels.
Introduces general level3 timer TIMER14 with two channels.
Introduces general level4 timers TIMER15 and TIMER16 with one channel.
Introduces basic timer TIMER5 with one channel.
Defines advanced timer registers, including base addresses and offsets.
Introduces IFRP for controlling infrared light LED and sending infrared data.
Lists IFRP output signal sources and configuration for high current capacity.
Explains IFRP integration with TIMER15 and TIMER16 for infrared ray signal generation.
Introduces USART for serial data exchange, supporting various modes and baud rate generation.
Lists USART features like NRZ format, full/half duplex, FIFO, dual clock domain, programmable baud rate.
Explains USART interface, modes like IrDA, smartcard, LIN, multiprocessor communication, and DMA support.
Defines USART registers, including base addresses and offsets.
Introduces I2C interface for MCU communication with external I2C devices using SDA and SCL.
Lists I2C features like master/slave functions, data transfer, addressing modes, speed modes, DMA support, and interrupt types.
Explains I2C module block diagram, SDA/SCL lines, data validation, START/STOP signals, clock synchronization, arbitration, and communication flow.
Defines I2C registers, including base addresses and offsets.
Introduces SPI and I2S modules for communication with external devices.
Lists SPI and I2S characteristics, including operation modes, data frame size, CRC, DMA, and audio standards.
Explains SPI block diagram, signal description, clock timing, data format, and NSS function.
Explains I2S block diagram, signal description, audio standards, clock generation, operation modes, and initialization.
Defines SPI registers, including base addresses and offsets.
Introduces HDMI-CEC controller for supporting CEC protocol in audio-visual products.
Lists HDMI-CEC controller features like compliance, clock sources, deep-sleep mode, SFT value, address, listen mode, and error detection.
Explains CEC bus pin configuration and message description.
Defines HDMI-CEC registers, including base addresses and offsets.
Introduces TSI for capacitive sensing applications using charge transfer method.
Lists TSI features like hardware-controlled sequence, parallel groups, IOs, frequency, and interrupts.
Explains TSI block diagram, touch sensing technique, charge transfer sequence, and clock durations.
Defines TSI registers, including base addresses and offsets.
Introduces USBFS controller for portable devices, supporting host, device, and OTG modes.
Lists USBFS features like host/device modes, OTG support, transfer types, FIFO RAM, and endpoints.
Shows the block diagram of the USBFS controller.
Describes USBFS signals like VBUS, DM, DP, and ID.
Explains USBFS clocks, working modes, host function, device function, and OTG function.
Lists USBFS interrupts: global interrupt and wake-up interrupt.
Lists revisions with dates, descriptions, and modifications made to the document.
General| Brand | GigaDevice Semiconductor |
|---|---|
| Model | GD32F3x0 |
| Category | Microcontrollers |
| Language | English |
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