GigaDevice Semiconductor GD32F3x0 - Figure 16-81. Timing Chart of Internal Clock Divided by 1

GD32F3x0 User Manual
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counter prescaler. When the CEN is set, the CK_TIMER will be divided by PSC value to
generate PSC_CLK.
Figure 16-81. Timing chart of internal clock divided by 1
CK_TIMER
CEN
PSC_CLK = TIMER_CK
CNT_REG
Reload Pulse
17 18 19 20 21 22
update event
generate(UPG)
23 00 01 02 03 04 05 06
07
Update event (UPE)
Clock prescaler
The counter clock (PSC_CK) is obtained by the TIMER_CK through the prescaler, and the
prescale factor can be configured from 1 to 65536 through the prescaler register
(TIMERx_PSC). The new written prescaler value will not take effect until the next update
event.