GigaDevice Semiconductor GD32F3x0 - Figure 21-4. Signal Free Time

GD32F3x0 User Manual
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Ts
Time (ms)
The bit start event.
T5
1.3ms
T5 as the earliest time that a device is allowed to return to a high
impedance state(logical 0).
T6
1.7ms
T6 as the latest time that a device is allowed to return to a high
impedance state(logical 0).
T7
2.05ms
T7 as the earliest time for the start of a following bit.
2.4ms
As a nominal data bit period.
T8
2.75ms
T8 as the latest time for the start of a following bit.
21.3.4. Arbitration
CEC line arbitration starts from the front edge of the start bit to the end of the Initiator
address bits among the Header Block. In the meantime the Initiator should monitor the CEC
line. During this period, if low impedance is detected when sending high impedance state
then it should assume that it has lost the arbitration.
|Arbitration Phase|
Bus
High
START Bit
INITIATOR[7:4]
DESTINATION[3:0]
END
OM
ACK
Bus
High
Before attempting to transmit or re-transmit a frame, a device shall ensure that the CEC line
has been inactive for a number of bit periods.
This signal free time is defined as the time since the start of the final bit of the previous
frame.
Figure 21-4. Signal Free Time
SFT of three nominal bit period
ACK bit of last frame of
previous message
Start bit of next
message
The length of the required signal free time depends on the current status of the control signal
line and the initiating device. If SFT=0x0, the HDMI-CEC controller’s SFT will perform as
table below:
Precondition
Signal Free Time (nominal data bit periods)
Present Initiator wants to send another message
immediately after its previous message
≥7