GigaDevice Semiconductor GD32F3x0 - Control Register 1 (CTC_CTL1)

GD32F3x0 User Manual
111
1: CTC trim counter enabled.
4
Reserved
Must be kept at reset value.
3
EREFIE
EREFIF interrupt enable
0: EREFIF interrupt disable
1: EREFIF interrupt enable
2
ERRIE
Error (ERRIF) interrupt enable
0: ERRIF interrupt disable
1: ERRIF interrupt enable
1
CKWARNIE
Clock trim warning (CKWARNIF) interrupt enable
0: CKWARNIF interrupt disable
1: CKWARNIF interrupt enable
0
CKOKIE
Clock trim OK (CKOKIF) interrupt enable
0: CKOKIF interrupt disable
1: CKOKIF interrupt enable
5.4.2. Control register 1 (CTC_CTL1)
Address offset: 0x04
Reset value: 0x2022 BB7F
This register has to be accessed by word (32-bit).
This register cannot be modified when CNTEN is 1.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
REF
POL
Reserved
REFSEL[1:0]
Reserved
REFPSC[2:0]
CKLIM[7:0]
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RLVALUE[15:0]
rw
Bits
Fields
Descriptions
31
REFPOL
Reference signal source polarity
This bit is set and cleared by software to select reference signal source polarity
0: rising edge selected
1: falling edge selected
30
Reserved
Must be kept at reset value.
29:28
REFSEL[1:0]
Reference signal source selection
These bits are set and cleared by software to select reference signal source.
00: GPIO selected
01: LXTAL clock selected