GigaDevice Semiconductor GD32F3x0 - I; O Compensation Control Register (SYSCFG_CPSCTL)

GD32F3x0 User Manual
38
LVDEN and LVDT[2:0] in the PMU_CTL register are read only.
1
SRAM_PARITY_
ERROR_LOCK
SRAM parity check error lock
This bit is set by software and cleared by a system reset.
0: The SRAM parity check error is disconnected from the break input of TIMER0 /
14 / 15 / 16
1: The SRAM parity check error is connected from the break input of TIMER0 / 14 /
15 / 16
0
LOCKUP_LOCK
Cortex
®
-M4 LOCKUP output lock
This bit is set by software and cleared by a system reset.
0: The Cortex
®
-M4 LOCKUP output is disconnected from the break input of
TIMER0 / 14 / 15 / 16
1: The Cortex
®
-M4 LOCKUP output is connected from the break input of TIMER0 /
14 / 15 / 16
1.6.7. I / O compensation control register (SYSCFG_CPSCTL)
Address offset: 0x20
Reset value: 0x0000 0000
This register has to be accessed by word (32-bit).
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
CPS_RD
Y
Reserved
CPS_EN
r
rw
Bits
Fields
Descriptions
31:9
Reserved
Must be kept at reset value.
8
CPS_RDY
I/O compensation cell is ready or not
This bit is read-only.
0: I/O compensation cell is not ready
1: I/O compensation cell is ready
7:1
Reserved
Must be kept at reset value.
0
CPS_EN
I/O compensation cell enable
0: I/O compensation cell is power-down
1: I/O compensation cell is enabled