GigaDevice Semiconductor GD32F3x0 - Reset Source;Clock Register (RCU_RSTSCK)

GD32F3x0 User Manual
96
4.3.10. Reset source /clock register (RCU_RSTSCK)
Address offset: 0x24
Reset value: 0x0C00 0000, reset flags reset by power Reset only, other reset by system
reset.
This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
LP
RSTF
WWDGT
RSTF
FWDGT
RSTF
SW
RSTF
POR
RSTF
EP
RSTF
OBL
RSTF
RSTFC
V12
RSTF
Reserved
r
r
r
r
r
r
r
rw
r
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
IRC40K
STB
IRC40K
EN
r
rw
Bits
Fields
Descriptions
31
LPRSTF
Low-power reset flag
Set by hardware when Deep-sleep /standby reset generated.
Reset by writing 1 to the RSTFC bit.
0: No Low-power management reset generated
1: Low-power management reset generated
30
WWDGTRSTF
Window watchdog timer reset flag
Set by hardware when a window watchdog timer reset generated.
Reset by writing 1 to the RSTFC bit.
0: No window watchdog reset generated
1: Window watchdog reset generated
29
FWDGTRSTF
Free Watchdog timer reset flag
Set by hardware when aFree Watchdog timer generated.
Reset by writing 1 to the RSTFC bit.
0: No Free Watchdog timer reset generated
1: Free Watchdog timer reset generated
28
SWRSTF
Software reset flag
Set by hardware when a software reset generated.
Reset by writing 1 to the RSTFC bit.
0: No software reset generated
1: Software reset generated
27
PORRSTF
Power reset flag
Set by hardware when a Power reset generated.
Reset by writing 1 to the RSTFC bit.
0: No Power reset generated