GigaDevice Semiconductor GD32F3x0 - Control Register 1 (DBG_CTL1)

GD32F3x0 User Manual
168
1
DSLP_HOLD
Deep-sleep mode hold bit
This bit is set and reset by software.
0: no effect
1: In the Deep-sleep mode, the clock of AHB bus and system clock are provided by
CK_IRC8M.
0
SLP_HOLD
Sleep mode hold bit
This bit is set and reset by software.
0: no effect
1: In the sleep mode, the clock of AHB is on.
10.4.3. Control register 1 (DBG_CTL1)
Address offset: 0x08
Reset value: 0x0000 0000, power reset only
This register has to be accessed by word(32-bit).
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved.
TIMER16
_HOLD
TIMER15
_HOLD
TIMER14
_HOLD
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
RTC_HO
LD
Reserved
rw
Bits
Fields
Descriptions
31:19
Reserved
Must be kept at reset value.
18
TIMER16_HOLD
TIMER16 hold bit
This bit is set and reset by software.
0: no effect
1: hold the TIMER16 counter for debugging when the core is halted.
17
TIMER15_HOLD
TIMER15 hold bit
This bit is set and reset by software.
0: no effect
1: hold the TIMER15 counter for debugging when the core is halted.
16
TIMER14_HOLD
TIMER14 hold bit
This bit is set and reset by software.
0: no effect
1: hold the TIMER14 counter for debugging when the core is halted.
15:11
Reserved
Must be kept at reset value.
10
RTC_HOLD
RTC hold bit
This bit is set and reset by software.
0: no effect