GigaDevice Semiconductor GD32F3x0 - APB1 Reset Register (RCU_APB1 RST)

GD32F3x0 User Manual
87
0: No reset
1: Reset the TIMER14
14
USART0RST
USART0 Reset
This bit is set and reset by software.
0: No reset
1: Reset the USART0
13
Reserved
Must be kept at reset value
12
SPI0RST
SPI0 Reset
This bit is set and reset by software.
0: No reset
1: Reset the SPI0
11
TIMER0RST
TIMER0 reset
This bit is set and reset by software.
0: No reset
1: Reset the TIMER0
10
Reserved
Must be kept at reset value
9
ADCRST
ADC reset
This bit is set and reset by software.
0: No reset
1: Reset the ADC
8:1
Reserved
Must be kept at reset value
0
CFGCMPRST
System configuration and comparator reset
This bit is set and reset by software.
0: No reset
1: Reset System configuration and comparator
4.3.5. APB1 reset register (RCU_APB1RST)
Address offset: 0x10
Reset value: 0x0000 0000
This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
CEC
RST
DAC
RST
PMU
RST
Reserved
I2C1
RST
I2C0
RST
Reserved
USART1
RST
Reserved
.
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
SPI1
RST
Reserved
WWDGT
RST
Reserved
TIMER13
RST
Reserved
TIMER5R
ST
Reserved
TIMER2
RST
TIMER1
RST
rw
rw
rw
rw
rw
rw