GigaDevice Semiconductor GD32F3x0 - Page 88

GD32F3x0 User Manual
88
Bits
Fields
Descriptions
31
Reserved
Must be kept at reset value
30
CECRST
HDMI CEC reset
This bit is set and reset by software.
0: No reset
1: Reset hdmi cec unit
29
DACRST
DAC reset
This bit is set and reset by software.
0: No reset
1: Reset DAC unit
28
PMURST
Power control reset
This bit is set and reset by software.
0: No reset
1: Reset power control unit
27:23
Reserved
Must be kept at reset value
22
I2C1RST
I2C1 reset
This bit is set and reset by software.
0: No reset
1: Reset I2C1
21
I2C0RST
I2C0 reset
This bit is set and reset by software.
0: No reset
1: Reset I2C0
20:18
Reserved
Must be kept at reset value
17
USART1RST
USART1 reset
This bit is set and reset by software.
0: No reset
1: Reset USART1
16:15
Reserved
Must be kept at reset value
14
SPI1RST
SPI1 reset
This bit is set and reset by software.
0: No reset
1: Reset SPI1
13:12
Reserved
Must be kept at reset value
11
WWDGTRST
Window watchdog timer reset
This bit is set and reset by software.
0: No reset