GigaDevice Semiconductor GD32F3x0 - Wait State Enable Register (FMC_WSEN); Product ID Register (FMC_PID)

GD32F3x0 User Manual
55
r
Bits
Fields
Descriptions
31:16
Reserved
Must be kept at reset value
15:0
OB_WP[15:0]
Store OB_WP[15:0] of option byte block after system reset
0: Protection active
1: Unprotected
2.4.9. Wait state enable register (FMC_WSEN)
Address offset: 0xFC
Reset value: 0x0000 0000
This register has to be accessed by word (32-bit)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
BPEN
WSEN
rw
rw
Bits
Fields
Descriptions
31:2
Reserved
Must be kept at reset value
1
BPEN
FMC bit program enable register
This bit set and reset by software.
0: No effect, write page must check if the flash is “FF”
1: Write page do not check if the flash is “FF”. The FMC can program each bit, the
written data is logically ANDed with the data stored in flash memory.
0
WSEN
FMC wait state enable register
This bit set and reset by software. This bit is also protected by the FMC_KEY
register. The software need writing 0x45670123 and 0xCDEF89AB to the
FMC_KEY register.
0: No wait state added when fetching flash
1: Wait state added when fetching flash
2.4.10. Product ID register (FMC_PID)
Address offset: 0x100
Reset value: 0xXXXX XXXX
This register has to be accessed by word (32-bit).
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16