GD32F3x0 User Manual
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4. Reset and clock unit (RCU)
4.1. Reset control unit (RCTL)
4.1.1. Overview
GD32F3x0 reset control includes the control of three kinds of reset: power reset, system
reset and backup domain reset. The power on reset, known as a cold reset, resets the full
system except the backup domain during a power up. A system reset resets the processor
core and peripheral IP components with the exception of the SW-DP controller and the
Backup domain. A backup domain reset resets the backup domain. The resets can be
triggered by an external signal, internal events and the reset generators. More information
about these resets will be described in the following sections.
4.1.2. Function overview
Power Reset
The power reset is generated by either an external reset as power on and power down reset
(POR/PDR reset), or by the internal reset generator when exiting standby mode. The power
reset sets all registers to their reset values except the backup domain. The power reset
which active signal is low will be de-asserted when the internal LDO voltage regulator is
ready to provide 1.2V power for GD32F3x0 series. The RESET service routine vector is fixed
at address 0x0000_0004 in the memory map.
System Reset
A system reset is generated by the following events:
A power reset (POWER_RSTn)
A external pin reset (NRST)
A window watchdog timer reset (WWDGT_RSTn)
A free watchdog timer reset (FWDGT_RSTn)
The SYSRESETREQ bit in Cortex
®
-M4 Application Interrupt and reset control register is
set (SW_RSTn)
Option byte loader reset (OBL_RSTn)
Reset generated when entering Standby mode when resetting nRST_STDBY bit in user
option bytes (OB_STDBY_RSTn)
Reset generated when entering deep-sleep mode when resetting nRST_DPSLP bit in
user option bytes (OB_DPSLP_RSTn)
A system reset resets the processor core and peripheral IP components except for the
SW-DP controller and the backup domain.
A system reset pulse generator guarantees low level pulse duration of 20 μs for each reset
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