GigaDevice Semiconductor GD32F3x0 - Configuration Register 2 (RCU_CFG2)

GD32F3x0 User Manual
100
1110: Input to PLL divided by 15
1111: Input to PLL divided by 16
4.3.13. Configuration register 2 (RCU_CFG2)
Address offset: 0x30
Reset value: 0x0000 0000
This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
ADCPS
C[2]
USBFSP
SC[2]
Reserved
IRC28MD
IV
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
ADCSEL
Reserved
CECSEL
Reserved
USART0SEL[1:0]
rw
rw
rw
Bits
Fields
Descriptions
31
ADCPSC[2]
Bit 2 of ADCPSC
see bits 15:14 of RCU_CFG0
30
USBFSPSC[2]
Bit 2 of USBFSPSC
see bits 23:22 of RCU_CFG0
29:17
Reserved
Must be kept at reset value
16
IRC28MDIV
IRC28M divider or not
0 : IRC28M /2 used as ADC clock
1: IRC28M used as ADC clock
15:9
Reserved
Must be kept at reset value
8
ADCSEL
CK_ADC clock source selection
This bit is set and reset by software.
0: CK_ADC select CK_IRC28M
1: CK_ADC select CK_APB2 which is divided by 2,4,6,8 or. CK_AHB which is
divided by 3,5,7,9
7
Reserved
Must be kept at reset value
6
CECSEL
CK_CEC clock source selection
This bit is set and reset by software.
0: CK_CEC select CK_IRC8M divided by 244
1: CK_CEC select CK_LXTAL
5:2
Reserved
Must be kept at reset value
1:0
USART0SEL[1:0]
CK_USART0 clock source selection