GigaDevice Semiconductor GD32F3x0 - APB2 Enable Register (RCU_APB2 EN)

GD32F3x0 User Manual
91
mode.
0: Disabled FMC clock during Sleep mode
1: Enabled FMC clock during Sleep mode
3
Reserved
Must be kept at reset value
2
SRAMSPEN
SRAM interface clock enable
This bit is set and reset by software to enable/disable SRAM interface clock during
Sleep mode.
0: Disabled SRAM interface clock during Sleep mode.
1: Enabled SRAM interface clock during Sleep mode
1
Reserved
Must be kept at reset value
0
DMAEN
DMA clock enable
This bit is set and reset by software.
0: Disabled DMA clock
1: Enabled DMA clock
4.3.7. APB2 enable register (RCU_APB2EN)
Address offset: 0x18
Reset value: 0x0000 0000
This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
TIMER16
EN
TIMER15
EN
TIMER14
EN
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
USART0
EN
Reserved
SPI0EN
TIMER0E
N
Reserved
ADCEN
Reserved
CFGCMP
EN
rw
rw
rw
rw
rw
Bits
Fields
Descriptions
31:19
Reserved
Must be kept at reset value
18
TIMER16EN
TIMER16 timer clock enable
This bit is set and reset by software.
0: Disabled TIMER16 timer clock
1: Enabled TIMER16 timer clock
17
TIMER15EN
TIMER15 timer clock enable
This bit is set and reset by software.
0: Disabled TIMER15 timer clock
1: Enabled TIMER15 timer clock