GigaDevice Semiconductor GD32F3x0 - Page 90

GD32F3x0 User Manual
90
0: Disabled TSI clock
1: Enabled TSI clock
23
Reserved
Must be kept at reset value
22
PFEN
GPIO port F clock enable
This bit is set and reset by software.
0: Disabled GPIO port F clock
1: Enabled GPIO port F clock
21
Reserved
Must be kept at reset value
20
PDEN
GPIO port D clock enable
This bit is set and reset by software.
0: Disabled GPIO port D clock
1: Enabled GPIO port D clock
19
PCEN
GPIO port C clock enable
This bit is set and reset by software.
0: Disabled GPIO port C clock
1: Enabled GPIO port C clock
18
PBEN
GPIO port B clock enable
This bit is set and reset by software.
0: Disabled GPIO port B clock
1: Enabled GPIO port B clock
17
PAEN
GPIO port A clock enable
This bit is set and reset by software.
0: Disabled GPIO port A clock
1: Enabled GPIO port A clock
16:13
Reserved
Must be kept at reset value
12
USBFSEN
USBFS clock enable
This bit is set and reset by software.
0: Disabled USBFS clock
1: Enabled USBFS clock
11:7
Reserved
Must be kept at reset value
6
CRCEN
CRC clock enable
This bit is set and reset by software.
0: Disabled CRC clock
1: Enabled CRC clock
5
Reserved
Must be kept at reset value
4
FMCSPEN
FMC clock enable
This bit is set and reset by software to enable/disable FMC clock during Sleep