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GigaDevice Semiconductor GD32F3x0 - Figure 16-13. Output-Compare under Three Modes

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GD32F3x0 User Manual
264
Figure 16-13. Output-compare under three modes
CEN
CNT_REG
00 01 02 03 04 05
.
62 63
Overflow
match toggle
CNT_CLK
OxCPRE
00 01 02 03 04 05
.
62 63
01 02 03 04 05
.
00
match set
match clear
OxCPRE
OxCPRE
Output PWM function
In the output PWM function (by setting the CHxCOMCTL bits to 3’b110 (PWM mode0) or to
3’b 111(PWM mode1), the channel can generate PWM waveform according to the
TIMERx_CAR registers and TIMERx_CHxCV registers.
Based on the counter mode, we can also divide PWM into EAPWM (Edge aligned PWM) and
CAPWM (Centre aligned PWM).
The EAPWM period is determined by TIMERx_CAR and duty cycle is determined by
TIMERx_CHxCV.Figure 16-14. EAPWM timechart shows the EAPWM output and
interrupts waveform.
The CAPWM period is determined by 2*TIMERx_CAR, and duty cycle is by
2*TIMERx_CHxCV. Figure 16-15. CAPWM timechart shows the CAPWM output and
interrupts waveform.
If TIMERx_CHxCV is greater than TIMERx_CAR, the output will be always active under
PWM mode0 (CHxCOMCTL==3’b110).
And if TIMERx_CHxCV is equal to zero, the output will be always inactive under PWM
mode0 (CHxCOMCTL==3’b110).

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