GigaDevice Semiconductor GD32F3x0 - Configuration Register 1 (RCU_CFG1)

GD32F3x0 User Manual
99
11:0
Reserved
Must be kept at reset value
4.3.12. Configuration register 1 (RCU_CFG1)
Address offset: 0x2C
Reset value: 0x0000 0000
This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
PLLMF[5]
PLLPRES
EL
Reserved
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
PREDV[3:0]
rw
Bits
Fields
Descriptions
31
PLLMF[5]
Bit 5 of PLLMF
see bits 27, 21:18 of RCU_CFG0
30
PLLPRESEL
PLL clock source preselection
0: HXTAL selected as PLL source clock
1: CK_IRC48M selected as PLL source clock
29:4
Reserved
Must be kept at reset value
3:0
PREDV[3:0]
CK_HXTAL or CK_IRC48M divider previous PLL
This bit is set and reset by software. These bits can be written when PLL is disable
Note: The bit 0 of PREDV is same as bit 17 of RCU_CFG0, so modifying bit 17 of
RCU_CFG0 aslo modifies bit 0 of RCU_CFG1.
The CK_HXTAL and CK_IRC48M is divided by (PREDV + 1).
0000: Input to PLL not divided
0001: Input to PLL divided by 2
0010: Input to PLL divided by 3
0011: Input to PLL divided by 4
0100: Input to PLL divided by 5
0101: Input to PLL divided by 6
0110: Input to PLL divided by 7
0111: Input to PLL divided by 8
1000: Input to PLL divided by 9
1001: Input to PLL divided by 10
1010: Input to PLL divided by 11
1011: Input to PLL divided by 12
1100: Input to PLL divided by 13
1101: Input to PLL divided by 14