2.3.11. Security protection
The FMC provides a security protection function to prevent illegal code/data access on the
flash memory. This function is useful for protecting the software/firmware from illegal users.
There are 3 levels for protecting:
No protection: when setting OB_SPC byte value to 0xA5, no protection performed. The main
flash and option bytes block are accessible by all operations.
Low level protection: when setting OB_SPC byte value to any value except 0xA5 and 0xCC,
protection level low performed. The main flash can only be accessed by user code. In debug
mode, boot from SRAM or boot from boot loader mode, all operations to main flash is
forbidden. If a read operation is executed to main flash in debug mode, boot from SRAM or
boot from boot loader mode, a bus error will be generated. If a program/erase operation is
executed to main flash in debug mode, boot from SRAM or boot from boot loader mode, the
PGERR bit in FMC_STAT register will be set. At low level protection, option bytes block are
accessible by all operations. If program back to no protection level by setting OB_SPC byte
value to 0xA5, a mass erase for main flash will be performed.
High level protection: when set OB_SPC byte value to 0xCC, high level protection performed.
When this level is programmed in debug mode, boot from SRAM or boot from boot loader
mode is disabled. The main flash block is accessible by all operations from user code. The
option byte cannot be erased, and the OB_SPC byte and its complement value cannot be
reprogrammed. So, if protection level high has been configured, it cannot move back to low
protection level or no protection level.
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