GigaDevice Semiconductor GD32F3x0 - APB2 Reset Register (RCU_APB2 RST)

GD32F3x0 User Manual
86
1: IRC8M stabilization interrupt generated
1
LXTALSTBIF
LXTAL stabilization interrupt flag
Set by hardware when the External 32.768 kHz crystal oscillator clock is stable and
the LXTALSTBIE bit is set.
Reset by software when setting the LXTALSTBIC bit.
0: No LXTAL stabilization interrupt generated
1: LXTAL stabilization interrupt generated
0
IRC40KSTBIF
IRC40K stabilization interrupt flag
Set by hardware when the Internal 32kHz RC oscillator clock is stable and the
IRC40KSTBIE bit is set.
Reset by software when setting the IRC40KSTBIC bit.
0: No IRC40K stabilization clock ready interrupt generated
1: IRC40K stabilization interrupt generated
4.3.4. APB2 reset register (RCU_APB2RST)
Address offset: 0x0C
Reset value: 0x0000 0000
This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
TIMER16
RST
TIMER15
RST
TIMER14
RST
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
USART0
RST
Reserved.
SPI0
RST
TIMER0
RST
Reserved
.
ADC
RST
Reserved
CFGCMP
RST
rw
rw
rw
rw
rw
Bits
Fields
Descriptions
31:19
Reserved
Must be kept at reset value
18
TIMER16RST
TIMER16 reset
This bit is set and reset by software.
0: No reset
1: Reset the TIMER16
17
TIMER15RST
TIMER15 reset
This bit is set and reset by software.
0: No reset
1: Reset the TIMER15
16
TIMER14RST
TIMER14 reset
This bit is set and reset by software.