GigaDevice Semiconductor GD32F3x0 - General Level2 Timer (Timerx, X=13); Overview; Characteristics; Figure 16-45. General Level2 Timer Block Diagram

GD32F3x0 User Manual
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16.3. General level2 timer (TIMERx, x=13)
16.3.1. Overview
The general level2 timer module (TIMER 13) is a one-channel timer that supports input
capture, output compare. They can generate PWM signals to control motor or be used for
power management applications. The general level2 time reference is a 16-bit counter that
can be used as an unsigned counter.
In addition, the general level2 timers can be programmed and be used to count or time
external events that drive other timers.
16.3.2. Characteristics
 Total channel num: 1.
 Counter width: 16-bit.
 Source of count clock: internal clock.
 Counter mode: count up only.
 Programmable prescaler: 16-bit. Factor can be changed on the go.
 Each channel is user-configurable:
Input capture mode, output compare mode, programmable and PWM mode.
 Auto-reload function.
 Interrupt output: update, compare/capture event.
16.3.3. Block diagram
Figure 16-45. General level2 timer block diagram provides details on the internal
configuration of the general level2 timer.
Figure 16-45. General level2 timer block diagram
Input Logic
Synchronizer&Filter
&Edge Detector
Prescaler
Trigger processor
Trigger Selector&Counter
Counter
TIMERx_CHxCV
Register /Interrupt
Register set and update
Interrupt collector
APB BUS
CK_TIMER
CH0_IN
CI0
CAR
Output Logic
generation of outputs signals in
compare, PWM,and mixed modes
according to initialization, software
output mask, and polarity control
CH0_O
Interrupt
Update
Cap/Com
PSC
TIMER_CK
PSC_CLK