GigaDevice Semiconductor GD32F3x0 - System and Memory Architecture; Arm Cortex-M4 Processor

GD32F3x0 User Manual
23
1. System and memory architecture
The GD32F3x0 series are 32-bit general-purpose microcontrollers based on the Arm
®
Cortex
®
-M4 processor. The Cortex
®
-M4 processor includes three AHB buses known as
I-Code, D-Code and System buses. All memory accesses of the Cortex
®
-M4 processor are
executed on the three buses according to the different purposes and the target memory
spaces. The memory organization uses the Harvard architecture, a pre-defined memory map
and up to 4 GB of memory space, making the system flexible and extendable.
1.1. Arm
®
Cortex
®
-M4 processor
The Cortex
®
-M4 processor is a 32-bit processor which is including the features of low
interrupt latency and low-cost debug. Integrated and advanced features make the
Cortex
®
-M4 processor suitable for market products that require microcontrollers with high
performance and low power consumption. The Cortex
®
-M4 processor is based on the Armv7
architecture and supports a powerful and scalable instruction set including general data
processing I / O control tasks and advanced data processing bit field manipulations. Some
system peripherals listed below are also provided by Cortex
®
-M4:
 Internal Bus Matrix connected with I-Code bus, D-Code bus, System bus, Private
Peripheral Bus (PPB) and debug accesses (AHB-AP).
 Nested Vectored Interrupt Controller (NVIC).
 Flash Patch and Breakpoint (FPB).
 Data Watchpoint and Trace (DWT).
 Instrumentation Trace Macrocell (ITM).
 Serial Wire Debug Port (SW-DP).
 Trace Port Interface Unit (TPIU).
 Floating Point Unit(FPU).
Figure 1-1. The structure of the Cortex
®
-M4 processor shows the Cortex
®
-M4 processor
block diagram. For more information, refer to the Arm
®
Cortex
®
-M4 Technical Reference
Manual.