GigaDevice Semiconductor GD32F3x0 - Control Register (FMC_CTL)

GD32F3x0 User Manual
52
BPEN = 1, no program error will be generated). The software can clear it by writing
1.
1
Reserved
Must be kept at reset value
0
BUSY
The flash busy bit
When the operation is in progress, this bit is set to 1. When the operation is end or
an error generated, this bit is clear to 0.
2.4.5. Control register (FMC_CTL)
Address offset: 0x10
Reset value: 0x0000 0080
This register has to be accessed by word (32-bit).
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
OBRLD
ENDIE
Reserved
ERRIE
OBWEN
Reserved
LK
START
OBER
OBPG
Reserved
MER
PER
PG
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits
Fields
Descriptions
31:14
Reserved
Must be kept at reset value
13
OBRLD
Option byte reload bit
This bit is set by software.
0: No effect
1: Force option byte reload, and generate a system reset
12
ENDIE
End of operation interrupt enable bit
This bit is set or cleared by software.
0: No interrupt generated by hardware
1: End of operation interrupt enable
11
Reserved
Must be kept at reset value
10
ERRIE
Error interrupt enable bit
This bit is set or cleared by software.
0: No interrupt generated by hardware
1: Error interrupt enable
9
OBWEN
Option byte erase/program enable bit
This bit is set by hardware when right sequence written to FMC_OBKEY register.
This bit can be cleared by software.
8
Reserved
Must be kept at reset value