GigaDevice Semiconductor GD32F3x0 - Table 21-3. TERR Timing Parameter Table

GD32F3x0 User Manual
561
High
Impedence
Low Impedence
Ts
Logic
0
Logic
1
1.5ms 2.4ms
T1
0.6ms
T2 T5
T3 T4 T6 T7 T8
2.4ms
Legend:
Checking
Window
TX data=0
Nominal sample time 1.05 ms
TX arb-bit=0/1
TX data=1
TX ack
High
Impedence
Low Impedence
Table 21-3. TERR Timing Parameter Table
Symbol
RTOL
Time(ms)
Description
Ts
-
0ms
The bit start event.
T1
1
0.3ms
The earliest time for a low - high transition when indicating a logical
1.
0
0.4ms
T2
0
0.8ms
The latest time for a low - high transition when indicating a logical 1.
1
0.9ms
T3
-
0.85ms
The earliest time it is safe to sample the signal line to determine its
state.
T4
-
1.25ms
The latest time it is safe to sample the signal line to determine its
state.
T5
1
1.2ms
The earliest time a device is permitted return to a high impedance
state (logical 0).
0
1.3ms
T6
0
1.7ms
The latest time a device is permitted return to a high impedance
state (logical 0).
1
1.8ms
T7
1
1.85ms
The earliest time for the start of a following bit.
0
2.05ms
2.4ms
The nominal data bit period.
T8
0
2.75ms
The latest time for the start of a following bit.
1
2.95ms
21.3.7. HDMI-CEC interrupt
There 13 interrupts in HDMI-CEC controller are made up of corresponding flag and interrupt
enable bit:
No.
Interrupt event in HDMI-CEC
Event flag
Interrupt enable bit
1
Arbitration fail
ARBF
ARBFIE
2
TX Byte Request
TBR
TBRIE
3
Transmission end
TEND
TENDIE