GigaDevice Semiconductor GD32F3x0 - Figure 20-45. PCM Standard Long Frame Synchronization Mode Timing Diagram (DTLEN=10, CHLEN=1, CKPL=0); Figure 20-46. PCM Standard Long Frame Synchronization Mode Timing Diagram (DTLEN=10, CHLEN=1, CKPL=1); Figure 20-47. PCM Standard Long Frame Synchronization Mode Timing Diagram (DTLEN=01, CHLEN=1, CKPL=0); Figure 20-48. PCM Standard Long Frame Synchronization Mode Timing Diagram (DTLEN=01, CHLEN=1, CKPL=1)

GD32F3x0 User Manual
535
Figure20-44. PCM standard long frame synchronization mode timing diagram
(DTLEN=00, CHLEN=0, CKPL=1)
I2S_CK
I2S_SD
16 bits
MSB
I2S_WS
MSB LSB
frame 1 frame 2
13 bits
Figure 20-45. PCM standard long frame synchronization mode timing diagram
(DTLEN=10, CHLEN=1, CKPL=0)
I2S_CK
I2S_SD
32 bits
MSB
I2S_WS
MSB LSB
frame 1 frame 2
13 bits
Figure 20-46. PCM standard long frame synchronization mode timing diagram
(DTLEN=10, CHLEN=1, CKPL=1)
I2S_CK
I2S_SD
32 bits
MSB
I2S_WS
MSB LSB
frame 1 frame 2
13 bits
Figure 20-47. PCM standard long frame synchronization mode timing diagram
(DTLEN=01, CHLEN=1, CKPL=0)
I2S_CK
I2S_SD
24-bit data
MSB
I2S_WS
MSB
frame 1 frame 2
13 bits
8-bit 0
Figure 20-48. PCM standard long frame synchronization mode timing diagram
(DTLEN=01, CHLEN=1, CKPL=1)
I2S_CK
I2S_SD
24-bit data
MSB
I2S_WS
MSB
frame 1 frame 2
13 bits
8-bit 0