GigaDevice Semiconductor GD32F3x0 - Table 19-1. Definition of I2 C-Bus Terminology (Refer to the I2 C Specification of Philips Semiconductors)

GD32F3x0 User Manual
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Figure 19-1. I2C module block diagram
Data Register
APB Bus
Shift RegisterSDA Controller
CRC Calculation /
Check
PEC register
SCL Controller
Timing and
Control Logic
Control Registers
Status Flags
SDA
SCL
DMA/ Interrupts
SMBA
Table 19-1. Definition of I2C-bus terminology (refer to the I2C specification of Philips
semiconductors)
Term
Description
Transmitter
The device which sends data to the bus
Receiver
The device which receives data from the bus
Master
The device which initiates a transfer, generates clock signals and
terminates a transfer
Slave
The device addressed by a master
Multi-master
More than one master can attempt to control the bus at the same time
without corrupting the message
Synchronization
Procedure to synchronize the clock signals of two or more devices
Arbitration
Procedure to ensure that, if more than one master tries to control the
bus simultaneously, only one is allowed to do so and the winning
master’s message is not corrupted
19.3.1. SDA and SCL lines
The I2C module has two external lines, the serial data SDA and serial clock SCL lines. The
two wires carry information between the devices connected to the bus.
Both SDA and SCL are bidirectional lines, connected to a positive supply voltage via
current-source or pull-up resistor. When the bus is free, both lines are HIGH. The output
stages of devices connected to the bus must have an open-drain or open-collect to perform
the wired-AND function. Data on the I2C-bus can be transferred at rates of up to 100 Kbit/s in
the standard mode, up to 400 Kbit/s in the fast mode and up to 1 Mbit/s in the fast-mode-plus