GigaDevice Semiconductor GD32F3x0 - Register Definition

GD32F3x0 User Manual
183
11.5. Register definition
ADC base address: 0x4001 2400
11.5.1. Status register (ADC_STAT)
Address offset: 0x00
Reset value: 0x0000 0000
This register has to be accessed by word (32-bit).
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
STRC
Reserved
EOC
WDE
rc_w0
rc_w0
rc_w0
Bits
Fields
Descriptions
31:5
Reserved
Must be kept at reset value.
4
STRC
Start flag of routine sequence conversion
0: Conversion is not started
1: Conversion is started
Set by hardware when routine sequence conversion starts. Cleared by software
writing 0 to it.
3:2
Reserved
Must be kept at reset value.
1
EOC
End flag of routine sequence conversion
0: No end of routine sequence conversion
1: End of routine sequence conversion
Set by hardware at the end of a routine sequence conversion.
Cleared by software writing 0 to it or by reading the ADC_RDATA register.
0
WDE
Analog watchdog event flag
0: No analog watchdog event
1: Analog watchdog event
Set by hardware when the converted voltage crosses the values programmed in
the ADC_WDLT and ADC_WDHT registers.
Cleared by software writing 0 to it.
11.5.2. Control register 0 (ADC_CTL0)
Address offset: 0x04
Reset value: 0x0000 0000