GigaDevice Semiconductor GD32F3x0 - Figure 20-53. I2 S Master Reception Disabling Sequence

GD32F3x0 User Manual
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Figure 20-53. I2S master reception disabling sequence
If DTLEN == 2b'00&&CHLEN ==
2b'1 && I2SSTDSEL ==2b'10 ?
Start
YES
Finish
Wait for the second last RBNE
Wait 17 I2S CK clock (clock on
I2S_CK pin) cycles
Clear the I2SEN bit
No
If DTLEN == 2b'00&&CHLEN ==
2b'1 && I2SSTDSEL !=2b'10 ?
Wait for the last RBNE
Wait one I2S clock cycle
Wait for the second last RBNE
Wait one I2S clock cycle
No
YES
I2S slave transmission sequence
The transmission sequence in slave mode is similar to that in master mode. The differences
between them are described below.
In slave mode, the slave has to be enabled before the external master starts the
communication. The transmission sequence begins when the external master sends the
clock and when the I2S_WS signal requests the transfer of data. The data has to be written
to the SPI_DATA register before the master initiates the communication. Software should
write the next audio data into SPI_DATA register before the current data finishes. Otherwise,
transmission underrun error occurs. The TXURERR flag is set and an interrupt may be
generated if the ERRIE bit in the SPI_CTL1 register is set. In this case, it is mandatory to
disable and enable I2S to resume the communication. In slave mode, I2SCH is sensitive to
the I2S_WS signal coming from the external master.
In order to disable I2S, it is mandatory to clear the I2SEN bit after the TBE flag is high and
the TRANS flag is low.