GD32F3x0 User Manual
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6. Interrupt/event controller (EXTI)
6.1. Overview
Cortex-M4 integrates the Nested Vectored Interrupt Controller (NVIC) for efficient exception
and interrupts processing. NVIC facilitates low-latency exception and interrupt handling and
controls power management. It’s tightly coupled to the processer core. You can read the
Technical Reference Manual of Cortex-M4 for more details about NVIC.
EXTI (interrupt/event controller) contains up to 24 independent edge detectors and
generates interrupt requests or events to the processer. The EXTI has three trigger types:
rising edge, falling edge and both edges. Each edge detector in the EXTI can be configured
and masked independently.
6.2. Characteristics
Cortex-M4 system exception
Up to 68 maskable peripheral interrupts for GD32F3x0 series
4 bits interrupt priority configuration - 16 priority levels
Efficient interrupt processing
Support exception pre-emption and tail-chaining
Wake up system from power saving mode
Up to 24 independent edge detectors in EXTI
Three trigger types: rising, falling and both edges
Software interrupt or event trigger
Trigger sources configurable
6.3. Interrupts function overview
The Arm Cortex-M4 processor and the Nested Vectored Interrupt Controller (NVIC) prioritize
and handle all exceptions in Handler Mode. The processor state is automatically stored to
the stack on an exception and automatically restored from the stack at the end of the
Interrupt Service Routine (ISR).
The vector is fetched in parallel to the state saving, enabling efficient interrupt entry. The
processor supports tail-chaining, which enables back-to-back interrupts to be performed
without the overhead of state saving and restoration. The following tables list all exception
types.
Table 6-1. NVIC exception types in Cortex-M4
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