GigaDevice Semiconductor GD32F3x0 - List of Figures

GD32F3x0 User Manual
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List of Figures
Figure 1-1. The structure of the Cortex
®
-M4 processor................................................................ 24
Figure 1-2. Series system architecture of GD32F3x0 series ....................................................... 25
Figure 2-1. Process of page erase operation .................................................................................. 43
Figure 2-2. Process of the mass erase operation .......................................................................... 44
Figure 2-3. Process of the word programming operation ............................................................ 46
Figure 3-1. Power supply overview .................................................................................................... 58
Figure 3-2. Waveform of the POR / PDR ........................................................................................... 60
Figure 3-3. Waveform of the LVD threshold .................................................................................... 60
Figure 4-1. The system reset circuit .................................................................................................. 71
Figure 4-2. Clock tree ............................................................................................................................ 72
Figure 4-3. HXTAL clock source ......................................................................................................... 73
Figure 4-4. HXTAL clock source in bypass mode .......................................................................... 74
Figure 5-1. CTC overview ................................................................................................................... 107
Figure 5-2. CTC trim counter ............................................................................................................. 108
Figure 6-1. Block diagram of EXTI ................................................................................................... 119
Figure 7-1. Basic structure of of a general-pupose I/O ............................................................... 126
Figure 7-2. Basic structure of Input configuration ....................................................................... 128
Figure 7-3. Basic structure of Output configuration ................................................................... 128
Figure 7-4. Basic structure of Analog configuration ................................................................... 129
Figure 7-5. Basic structure of Alternate function configuration .............................................. 129
Figure 8-1. Block diagram of CRC calculation unit ..................................................................... 144
Figure 9-1. Block diagram of DMA ................................................................................................... 150
Figure 9-2. Handshake mechanism ................................................................................................. 152
Figure 9-3. DMA interrupt logic ......................................................................................................... 154
Figure 9-4. DMA request mapping.................................................................................................... 156
Figure 11-1. ADC module block diagram ........................................................................................ 172
Figure 11-2. Single operation mode ................................................................................................. 173
Figure 11-3. Continuous operation mode ...................................................................................... 174
Figure 11-4. Scan operation mode, continuous disable ............................................................. 175
Figure 11-5. Scan operation mode, continuous enable .............................................................. 175
Figure 11-6. Discontinuous operation mode ................................................................................. 176
Figure 11-7. Data storage mode of 12-bit resolution ................................................................... 177
Figure 11-8. Data storage mode of 10-bit resolution ................................................................... 177
Figure 11-9. Data storage mode of 8-bit resolution ..................................................................... 177
Figure 11-10. Data storage mode of 6-bit resolution ................................................................... 177
Figure 11-11. 20-bit to 16-bit result truncation .............................................................................. 180
Figure 11-12. Numerical example with 5-bits shift and rounding ............................................ 181
Figure 12-1. DAC block diagram ....................................................................................................... 194
Figure 12-2. DAC LFSR algorithm .................................................................................................... 196
Figure 12-3. DAC triangle noise wave ............................................................................................. 197