GD32F3x0 User Manual
76
System Clock (CK_SYS) Selection
After the system reset, the default CK_SYS source will be IRC8M and can be switched to
HXTAL or PLL by changing the system clock switch bits, SCS, in the Configuration register 0,
RCU_CFG0. When the SCS value is changed, the CK_SYS will continue to operate using
the original clock source until the target clock source is stable. When a clock source is used
directly by the CK_SYS or the PLL, it is not possible to stop it.
HXTAL Clock Monitor (CKM)
The HXTAL clock monitor function is enabled by the HXTAL clock monitor enable bit,
CKMEN, in the control register 0, RCU_CTL0. This function should be enabled after the
HXTAL start-up delay and disabled when the HXTAL is stopped. Once the HXTAL failure is
detected, the HXTAL will be automatically disabled. The HXTAL clock stuck flag, CKMIF, in
the interrupt register, RCU_INT, will be set and the HXTAL failure event will be generated.
This failure interrupt is connected to the non-maskable interrupt, NMI, of the Cortex-M4. If
the HXTAL is selected as the clock source of CK_SYS or PLL, the HXTAL failure will force
the CK_SYS source to IRC8M and the PLL will be disabled automatically.
Clock Output Capability
The clock output capability is ranging from 32 kHz to 108 MHz. There are several clock
signals can be selected via the CK_OUT clock source selection bits, CKOUTSEL, in the
configuration register 0(RCU_CFG0). The corresponding GPIO pin should be configured in
the properly alternate function I/O (AFIO) mode to output the selected clock signal.
Table 4-1. Clock source select
The CK_OUT frequency can be reduced by a configurable binary divider, controlled by the
CKOUTDIV[2:0] bits , in the Configuration register 0(RCU_CFG0).
Deep-sleep mode clock control
When the MCU is in deep-sleep mode, the HDMI CEC or USART0 can wake up the MCU,
when their clock is provided by LXTAL clock and LXTAL clock is enable.
If the HDMI CEC or USART0 clock is selected IRC8M clock in deep-sleep mode, they have
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