GigaDevice Semiconductor GD32F3x0 - Control Register 1 (RCU_CTL1); Additional Clock Control Register (RCU_ADDCTL)

GD32F3x0 User Manual
101
This bit is set and reset by software.
00: CK_USART0 select CK_APB2
01: CK_USART0 select CK_SYS
10: CK_USART0 select CK_LXTAL
11: CK_USART0 select CK_IRC8M
4.3.14. Control register 1 (RCU_CTL1)
Address offset: 0x34
Reset value: 0x0000 XX80 where X is undefined.
This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
IRC28MCALIB[7:0]
IRC28MADJ[4:0]
Reserved
IRC28MS
TB
IRC28ME
N
r
rw
r
rw
Bits
Fields
Descriptions
31:16
Reserved
Must be kept at reset value
15:8
IRC28MCALIB[7:0]
Internal 28M RC Oscillator calibration value register
These bits are load automatically at power on.
7:3
IRC28MADJ[4:0]
Internal 28M RC Oscillator clock trim adjust value
These bits are set by software. The trimming value is there bits (IRC28MADJ)
added to the IRC28MCALIB[7:0] bits. The trimming value should trim the IRC28M
to 28MHz ± 1%.
2
Reserved
Must be kept at reset value
1
IRC28MSTB
IRC28M Internal 28M RC Oscillator stabilization Flag
Set by hardware to indicate if the IRC28M oscillator is stable and ready for use.
0: IRC28M oscillator is not stable
1: IRC28M oscillator is stable
0
IRC28MEN
IRC28M Internal 28M RC oscillator Enable
Set and reset by software.
0: Internal 28 MHz RC oscillator disabled
1: Internal 28 MHz RC oscillator enabled
4.3.15. Additional clock control register (RCU_ADDCTL)
Address offset: 0xC0