GigaDevice Semiconductor GD32F3x0 - Table 4-2. Core Domain Voltage Selected in Deep-Sleep Mode

GD32F3x0 User Manual
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capable of open IRC8M clock or close IRC8M clock, which used to the HDMI CEC or
USART0 to wake up the Deep-sleep mode.
Voltage control
The core domain voltage in deep-sleep mode can be controlled by DSLPVS[1:0] bit in the
deep-sleep mode voltage register (RCU_DSV).
Table 4-2. Core domain voltage selected in Deep-sleep mode
DSLPVS[1:0]
Deep-sleep mode voltage(V)
00
default value
01
(default value-0.1)
10
(default value-0.2)
11
(default value-0.3)
The RCU_DSV register are protected by Voltage Key register (RCU_VKEY). Only after write
0x1A2B3C4D to the RCU_VKEY register, the RCU_DSV register can be write.