GD32F3x0 User Manual
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ITI0/1/2/3. This mode can be selected by setting SMC [2:0] to 0x7 and the TRGS [2:0] to 0x0,
0x1, 0x2 or 0x3.
Clock prescaler
The counter clock (PSC_CK) is obtained by the TIMER_CK through the prescaler, and the
prescale factor can be configured from 1 to 65536 through the prescaler register
(TIMERx_PSC). The new written prescaler value will not take effect until the next update
event.
Figure 16-55. Timing chart of PSC value change from 0 to 2
Counter up counting
In this mode, the counter counts up continuously from 0 to the counter-reload value, which is
defined in the TIMERx_CAR register, in a count-up direction. Once the counter reaches the
counter reload value, the counter will start counting up from 0 again and an overflow event
will be generated. In addition, the update events will be generated after (TIMERx_CREP+1)
times of overflow events. The counting direction bit DIR in the TIMERx_CTL0 register should
be set to 0 for the up counting mode.
Whenever, if the update event software trigger is enabled by setting the UPG bit in the
TIMERx_SWEVG register, the counter value will be initialized to 0 and generates an update
event.
If set the UPDIS bit in TIMERx_CTL0 register, the update event is disabled.
When an update event occurs, all the shadow registers (repetition counter, counter auto
reload register, prescaler register) are updated.
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