GigaDevice Semiconductor GD32F3x0 - DAC 8-Bit Right-Aligned Data Holding Register (DAC_R8 DH); DAC Data Output Register (DAC_DO); DAC Status Register (DAC_STAT)

GD32F3x0 User Manual
201
12.4.5. DAC 8-bit right-aligned data holding register (DAC_R8DH)
Address offset: 0x10
Reset value: 0x0000 0000
This register has to be accessed by word(32-bit)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
DAC_DH[7:0]
rw
Bits
Fields
Descriptions
31:8
Reserved
Must be kept at reset value.
7:0
DAC_DH[7:0]
DAC 8-bit right-aligned data
These bits specify the MSB 8 bits of the data that is to be converted by DAC.
12.4.6. DAC data output register (DAC_DO)
Address offset: 0x2C
Reset value: 0x0000 0000
This register has to be accessed by word (32-bit).
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
DAC_DO [11:0]
r
Bits
Fields
Descriptions
31:12
Reserved
Must be kept at reset value.
11:0
DAC_DO [11:0]
DAC data output
These bits, which are read only, reflect the data that is being converted by DAC.
12.4.7. DAC Status register (DAC_STAT)
Address offset: 0x34
Reset value: 0x0000 0000
This register has to be accessed by word (32-bit).
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16