1.3. Memory map
The Arm
®
Cortex
®
-M4 processor is structured in Harvard architecture which can use
separate buses to fetch instructions and load/store data. The instruction code and data are
both located in the same memory address space but in different address ranges. Program
memory, data memory, registers and I / O ports are organized within the same linear
4-Gbyte address space which is the maximum address range of the Cortex
®
-M4 since it has
a 32-bit bus address width. Additionally, a pre-defined memory map is provided by the
To Next Page
