GigaDevice Semiconductor GD32F30 Series

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Overview

This document describes the GD32F30x series of 32-bit general-purpose microcontrollers, which are based on the Arm® Cortex®-M4 processor. The Cortex®-M4 processor is a 32-bit unit designed for low interrupt latency and efficient debugging, making it suitable for high-performance and low-power applications. It utilizes a Harvard architecture with three AHB buses (I-Code, D-Code, and System) for memory access, offering a flexible and expandable system with up to 4 GB of memory space. Key system peripherals include an internal Bus Matrix, Nested Vectored Interrupt Controller (NVIC), Flash Patch and Breakpoint (FPB), Data Watchpoint and Trace (DWT), Instrumentation Trace Macrocell (ITM), Serial Wire JTAG Debug Port (SWJ-DP), Trace Port Interface Unit (TPIU), Memory Protection Unit (MPU), and Floating Point Unit (FPU).

The device features a Flash Memory Controller (FMC) that supports up to 3072KB of on-chip flash memory for instructions and data, with no waiting time for CPU instruction execution within the first 256KB. It includes 2KB page sizes for Bank0 (first 512KB) and 4KB for Bank1 (remaining capacity) in GD32F30x_CL and GD32F30x_XD devices, allowing individual page erase, mass erase, and word/half-word/bit programming. The FMC also incorporates a 16B option bytes block for user application requirements, flash security protection against illegal code/data access, and page erase/program protection to prevent unintended operations.

Power management is handled by the PMU, offering three power domains (VBAK, VDD/VDDA, and 1.2V) and three power-saving modes: Sleep, Deep-sleep, and Standby. The internal LDO supplies the 1.2V domain, and a Low Voltage Detector (LVD) can trigger an interrupt or event if the supply voltage drops below a set threshold. The Backup domain, powered by VDD or VBAT, retains data in 84 bytes of backup registers even when VDD is off. These registers also support RTC clock calibration and tamper detection.

The Reset and Clock Unit (RCU) manages various clock sources, including internal 8MHz (IRC8M) and 48MHz (IRC48M) RC oscillators, a High-Speed Crystal (HXTAL) from 4 to 32 MHz, a Low-Speed Crystal (LXTAL) at 32.768 Hz, and a Low-Speed Internal 40KHz (IRC40K) RC oscillator. It also includes a Phase-Locked Loop (PLL), HXTAL clock monitor, and configurable clock prescalers and multiplexers. The system clock (CK_SYS) can operate up to 120 MHz, with AHB, APB1, and APB2 clocks derived from it. The Clock Trim Controller (CTC) automatically trims the IRC48M frequency based on an external reference signal, ensuring precise clock operation.

The External Interrupt/Event Controller (EXTI) provides up to 20 independent edge detectors for generating interrupt requests or events, supporting rising, falling, and both edge triggers. GPIO and AFIO units offer up to 112 general-purpose I/O pins, configurable as output (push-pull or open-drain), input (floating, pull-down/pull-up), or alternate function. The GPIO locking function protects I/O configurations, and an I/O compensation cell can be enabled for high-speed output (over 50MHz) to reduce noise.

The Cyclic Redundancy Check (CRC) management unit calculates 32-bit CRC codes with a fixed polynomial (0x4C11DB7), commonly used in Ethernet, and includes an 8-bit free data register. The Direct Memory Access Controller (DMA) has 12 channels (7 for DMA0, 5 for DMA1) for efficient data transfers between peripherals and memory, supporting programmable data lengths, various transfer widths (8, 16, 32-bit), circular mode, and memory-to-memory transfers. Each channel has a dedicated interrupt with three event flags.

The Debug (DBG) unit provides JTAG/SWD debug and trace functions, including support for power-saving modes and holding peripheral states (TIMER, I2C, WWDGT, FWDGT, CAN) during core halts. The Analog-to-Digital Converter (ADC) is a 12-bit successive approximation module with 16 external and 2 internal sampling channels, supporting various operation modes (single, continuous, scan, discontinuous, sync), programmable resolution (12, 10, 8, 6-bit), and on-chip hardware oversampling. The Digital-to-Analog Converter (DAC) converts 12-bit digital data to analog voltage, supporting 8-bit or 12-bit resolution, DMA, external triggers, and noise wave generation (LFSR or Triangle).

Watchdog timers include a Free Watchdog Timer (FWDGT) with a free-running 12-bit downcounter and a Window Watchdog Timer (WWDGT) with a 7-bit downcounter, both designed to detect software malfunctions and generate resets. The Real-Time Clock (RTC) provides clock-calendar functions with a 32-bit programmable counter, prescaler, and divider, maintaining time and settings even during power-saving modes.

Multiple Timer (TIMERx) modules are available, categorized into Advanced (TIMER0/7), General Level0 (TIMER1-4), General Level1 (TIMER8/11), General Level2 (TIMER9/10/12/13), and Basic (TIMER5/6) timers. These timers offer 16-bit counters, various counter modes (up, down, center-aligned), programmable prescalers, input capture, output compare, PWM generation, dead-time insertion, auto-reload, repetition functions, break input, and master-slave management.

The Universal Synchronous/Asynchronous Receiver/Transmitter (USART) provides flexible serial data exchange, supporting full-duplex or half-duplex, synchronous or asynchronous modes, programmable baud rates (up to 7.5 MBits/s), various data word lengths (8 or 9 bits), stop bits, hardware flow control (CTS/RTS), LIN mode, IrDA SIR ENDEC mode, and ISO 7816-3 smartcard interface. The Inter-Integrated Circuit Interface (I2C) supports standard, fast, and fast-mode-plus protocols, 7-bit and 10-bit addressing, multi-master capability, SCL stretching, DMA mode, SMBus/PMBus compatibility, and Packet Error Checking (PEC).

The Serial Peripheral Interface/Inter-IC Sound (SPI/I2S) module supports SPI protocol in master or slave mode (full-duplex or simplex), 8 or 16-bit data frames, LSB/MSB first bit order, hardware CRC, and Quad-SPI master mode (SPI0 only). The I2S audio protocol supports Phillips, MSB justified, LSB justified, and PCM standards, with data lengths of 16, 24, or 32 bits, and audio sample frequencies from 8 kHz to 192 kHz.

The Secure Digital Input/Output Interface (SDIO) defines host interfaces for SD, SD I/O, MMC, and CE-ATA cards, supporting 1-bit, 4-bit, and 8-bit data bus modes, up to 48MHz data transfer, interrupt, and DMA requests. The External Memory Controller (EXMC) acts as a translator for accessing external SRAM, ROM, NOR Flash, NAND Flash, and PC Card, with configurable timing parameters and ECC hardware for NAND Flash. The Controller Area Network (CAN) supports CAN protocols 2.0A and B, baud rates up to 1 Mbit/s, time-triggered communication, 3 transmit mailboxes, 2 Rx FIFOs, and scalable identifier filter banks. The Universal Serial Bus Full-Speed Device Interface (USBD) provides a USB 2.0 full-speed compliant peripheral solution, supporting 8 configurable bidirectional endpoints, double-buffered bulk/isochronous transfers, USB 2.0 Link Power Management, and an integrated USB PHY. The Universal Serial Bus Full-Speed Interface (USBFS) offers host, device, and OTG modes, supporting USB 2.0 full-speed (12Mb/s) and low-speed (1.5Mb/s) operations, 4 types of transfers, a 1.25KB FIFO RAM, and an integrated full-speed USB PHY.