GigaDevice Semiconductor GD32E50 Series User Manual (English)

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GigaDevice Semiconductor Inc.

GD32E50x

Arm

Cortex

-M33 32-bit MCU

For GD32E503xx, GD32E505xx, GD32E507xx, GD32E508xx,

GD32EPRTxx

User Manual

Revision 1.7

(Jun. 2022)

Table of Contents2
List of Figures21
List of Tables31
System and Memory Architecture36
Arm ® Cortex ® -M33 Processor36
Figure 1-1. the Structure of the Cortex ® -M33 Processor36
System Architecture37
Table 1-1. the Interconnection Relationship of the AHB Interconnect Matrix37
Memory Map39
Figure 1-2. Gd32E50X System Architecture39
Table 1-2. Memory Map of Gd32E50X Devices40
On-Chip SRAM Memory43
On-Chip Flash Memory Overview43
Boot Configuration44
Device Electronic Signature44
Table 1-3. Boot Modes44
Memory Density Information45
Unique Device ID (96 Bits)45
System Configuration Registers46
Flash Memory Controller (FMC)47
Overview47
Characteristics47
Function Overview47
Flash Memory Architecture47
Table 2-1. Gd32E50X_Hd and Gd32E50X_Cl Base Address and Size for Flash Memory47
Read Operations48
Table 2-2. the Relation between WSCNT and AHB Clock Frequency48
Unlock the FMC_CTL Register49
Page Erase50
Mass Erase51
Figure 2-1. Process of Page Erase Operation51
Main Flash Programming52
Figure 2-2. Process of Mass Erase Operation52
OTP Programming54
Option Bytes Erase54
Figure 2-3. Process of Word Program Operation54
Option Bytes Modify55
Option Bytes Description55
Table 2-3. Option Bytes56
Page Erase / Program Protection57
Security Protection57
Table 2-4. OB_WP Bit for Pages Protected57
Register Definition58
Wait State Register (FMC_WS)58
Unlock Key Register (FMC_KEY)59
Option Byte Unlock Key Register (FMC_OBKEY)59
Status Register (FMC_STAT)60
Control Register (FMC_CTL)61
Address Register (FMC_ADDR)62
Option Byte Status Register (FMC_OBSTAT)62
Erase/Program Protection Register (FMC_WP)63
Product ID Register (FMC_PID)63
Backup Registers (BKP)65
Overview65
Characteristics65
Function Overview65
RTC Clock Calibration65
Tamper Detection65
Register Definition67
Backup Data Register X (Bkp_Datax) (X= 067
RTC Signal Output Control Register (BKP_OCTL)67
Tamper Pin Control Register (BKP_TPCTL)68
Tamper Control and Status Register (BKP_TPCS)69
Power Management Unit (PMU)70
Overview70
Characteristics70
Function Overview70
Figure 4-1. Power Supply Overview70
Backup Domain71
VDD / V Dda72
Figure 4-2. Waveform of the por / PDR72
Figure 4-3. Waveform of the BOR73
Figure 4-4. Waveform of the LVD Threshold74
1.1V Power Domain75
Power Saving Modes75
Table 4-1. Power Saving Mode Summary78
Register Definition80
Control Register 0 (PMU_CTL0)80
Control and Status Register 0 (PMU_CS0)82
Control Register 1 (PMU_CTL1)84
Control and Status Register 1 (PMU_CS1)85
Reset and Clock Unit (RCU)86
High Density Reset and Clock Control Unit (RCU)86
Reset Control Unit (RCTL)86
Overview86
Function Overview86
Clock Control Unit (CCTL)87
Overview87
Figure 5-1. the System Reset Circuit87
Figure 5-2. Clock Tree88
Characteristics89
Function Overview89
Figure 5-3. HXTAL Clock Source90
Figure 5-4. HXTAL Clock Source in Bypass Mode90
Table 5-1. Clock Output 0 Source Select93
Table 5-2. 1.1V Domain Voltage Selected in Deep-Sleep Mode93
Register Definition94
Control Register (RCU_CTL)94
Clock Configuration Register 0 (RCU_CFG0)95
Clock Interrupt Register (RCU_INT)99
APB2 Reset Register (RCU_APB2RST)101
APB1 Reset Register (RCU_APB1RST)104
AHB Enable Register (RCU_AHBEN)107
APB2 Enable Register (RCU_APB2EN)108
APB1 Enable Register (RCU_APB1EN)111
Backup Domain Control Register (RCU_BDCTL)114
Reset Source/Clock Register (RCU_RSTSCK)115
AHB Reset Register (RCU_AHBRST)117
Clock Configuration Register 1 (RCU_CFG1)118
Deep-Sleep Mode Voltage Register (RCU_DSV)118
Additional Clock Control Register (RCU_ADDCTL)119
Additional Clock Interrupt Register (RCU_ADDINT)120
PLL Clock Spread Spectrum Control Register (RCU_PLLSSCTL)120
Clock Configuration Register 2 (RCU_CFG2)121
APB1 Additional Reset Register (RCU_ADDAPB1RST)122
APB1 Additional Enable Register (RCU_ADDAPB1EN)122
Connectivity Line Devices: Reset and Clock Control Unit (RCU)124
Reset Control Unit (RCTL)124
Overview124
Function Overview124
Clock Control Unit (CCTL)125
Overview125
Figure 5-5. the System Reset Circuit125
Figure 5-6. Clock Tree126
Characteristics127
Function Overview128
Figure 5-7. HXTAL Clock Source128
Figure 5-8. HXTAL Clock Source in Bypass Mode128
Table 5-3. Clock Output 0 Source Select131
Table 5-4. 1.1V Domain Voltage Selected in Deep-Sleep Mode132
Register Definition133
Control Register (RCU_CTL)133
Clock Configuration Register 0 (RCU_CFG0)135
Clock Interrupt Register (RCU_INT)138
APB2 Reset Register (RCU_APB2RST)142
APB1 Reset Register (RCU_APB1RST)144
AHB Enable Register (RCU_AHBEN)147
APB2 Enable Register (RCU_APB2EN)149
APB1 Enable Register (RCU_APB1EN)152
Backup Domain Control Register (RCU_BDCTL)155
Reset Source/Clock Register (RCU_RSTSCK)156
AHB Reset Register (RCU_AHBRST)158
Clock Configuration Register 1 (RCU_CFG1)159
Deep-Sleep Mode Voltage Register (RCU_DSV)162
Additional Clock Control Register (RCU_ADDCTL)162
Additional Clock Configuration Register (RCU_ADDCFG)164
Additional Clock Interrupt Register (RCU_ADDINT)165
PLL Clock Spread Spectrum Control Register (RCU_PLLSSCTL)166
Clock Configuration Register 2 (RCU_CFG2)167
APB1 Additional Reset Register (RCU_ADDAPB1RST)168
APB1 Additional Enable Register (RCU_ADDAPB1EN)168
Clock Trim Controller (CTC)170
Overview170
Characteristics170
Function Overview170
Figure 6-1. CTC Overview170
REF Sync Pulse Generator171
CTC Trim Counter171
Frequency Evaluation and Automatically Trim Process172
Figure 6-2. CTC Trim Counter172
Software Program Guide173
Register Definition175
Control Register 0 (CTC_CTL0)175
Control Register 1 (CTC_CTL1)176
Status Register (CTC_STAT)177
Interrupt Clear Register (CTC_INTC)179
Interrupt/Event Controller (EXTI)181
Overview181
Characteristics181
Interrupts Function Overview181
Table 7-1. NVIC Exception Types in Cortex ® -M33182
Table 7-2. Interrupt Vector Table182
External Interrupt and Event (EXTI) Block Diagram186
External Interrupt and Event Function Overview186
Figure 7-1. Block Diagram of EXTI186
Table 7-3. EXTI Source186
EXTI Register189
Interrupt Enable Register (EXTI_INTEN)189
Event Enable Register (EXTI_EVEN)189
Rising Edge Trigger Enable Register (EXTI_RTEN)190
Falling Edge Trigger Enable Register (EXTI_FTEN)190
Software Interrupt Event Register (EXTI_SWIEV)190
Pending Register (EXTI_PD)191
General-Purpose and Alternate-Function I/Os (GPIO and AFIO)192
Overview192
Characteristics192
Function Overview192
GPIO Pin Configuration193
Figure 8-1. Basic Structure of a General-Pupose I/O193
Table 8-1. GPIO Configuration Table193
External Interrupt/Event Lines194
Alternate Functions (AF)194
Input Configuration194
Figure 8-2. Basic Structure of Input Configuration194
Output Configuration195
Analog Configuration195
Figure 8-3. Basic Structure of Output Configuration195
Figure 8-4. Basic Structure of Analog Configuration195
Alternate Function (AF) Configuration196
IO Pin Function Selection196
Figure 8-5. Basic Structure of Alternate Function Configuration196
GPIO Locking Function197
GPIO I/O Compensation Cell197
Remapping Function I/O and Debug Configuration197
Introduction197
Main Features197
JTAG/SWD Alternate Function Remapping198
ADC AF Remapping198
Table 8-2. Debug Interface Signals198
Table 8-3. Debug Port Mapping and Pin Availability198
Table 8-4. ADC0/1 External Trigger Routine Conversion AF Remapping Function198
TIMER AF Remapping199
Table 8-5. Timerx Alternate Function Remapping199
USART AF Remapping200
Table 8-6. TIMER4 Alternate Function Remapping200
Table 8-7. USART0/1/2 Alternate Function Remapping200
I2C0 AF Remapping201
SPI0/SPI2/I2S AF Remapping201
Table 8-8. I2C0 Alternate Function Remapping201
CAN0/1 AF Remapping202
Table 8-9. SPI0/SPI2/I2S Alternate Function Remapping202
Table 8-10. CAN0/1 Alternate Function Remapping202
Ethernet AF Remapping203
CTC AF Remapping203
CLK Pins AF Remapping203
Table 8-11. ENET Alternate Function Remapping203
Table 8-12. CTC Alternate Function Remapping203
Table 8-13. OSC32 Pins Configuration203
Table 8-14. OSC Pins Configuration203
Register Definition205
Port Control Register 0 (Gpiox_Ctl0, X=A205
Port Control Register 1 (Gpiox_Ctl1, X=A207
Port Input Status Register (Gpiox_Istat, X=A208
Port Output Control Register (Gpiox_Octl, X=A209
Port Bit Operate Register (Gpiox_Bop , X=A209
Port Bit Clear Register (Gpiox_Bc, X=A210
Port Configuration Lock Register (Gpiox_Lock, X=A210
Port Bit Speed Register (Gpiox_ SPD, X=A211
Event Control Register (AFIO_EC)212
AFIO Port Configuration Register 0 (AFIO_PCF0)212
EXTI Sources Selection Register 0 (AFIO_EXTISS0)219
EXTI Sources Selection Register 1 (AFIO_EXTISS1)220
EXTI Sources Selection Register 2 (AFIO_EXTISS2)221
EXTI Sources Selection Register 3 (AFIO_EXTISS3)222
AFIO Port Configuration Register 1 (AFIO_PCF1)224
IO Compensation Control Register (AFIO_CPSCTL)225
AFIO Port Configuration Register a (AFIO_PCFA)226
AFIO Port Configuration Register B (AFIO_PCFB)228
AFIO Port Configuration Register C (AFIO_PCFC)230
AFIO Port Configuration Register D (AFIO_PCFD)232
AFIO Port Configuration Register E (AFIO_PCFE)233
AFIO Port Configuration Register G (AFIO_PCFG)234
Cyclic Redundancy Checks Management Unit (CRC)237
Overview237
Characteristics237
Figure 9-1. Block Diagram of CRC Management Unit237
Function Overview238
Register Definition239
Data Register (CRC_DATA)239
Free Data Register (CRC_FDATA)239
Control Register (CRC_CTL)240
Initialization Data Register (CRC_IDATA)240
Polynomial Register (CRC_POLY)241
Trigonometric Math Unit (TMU)242
Overview242
Characteristics242
Function Overview242
TMU Block Diagram242
Table 10-1. 9 Different Operation Modes242
Data Format243
Figure 10-1. Block Diagram of Trigonometric Math Unit243
Table 10-2. IEEE 32-Bit Single Precision Floating-Point Format243
Mode 0 Description244
Mode 1 Description244
Table 10-3. Convert Per-Unit Values to Radians in Mode 0244
Table 10-4. Convert Radians Values to Per-Unit Values in Mode 1244
Mode 2 Description245
Mode 3 Description245
Mode 4 Description245
Mode 5 Description246
Mode 6 Description246
Table 10-5. the Range of Input Value and R0 Value in Mode 5246
Figure 10-2. Calculation of R1 (Quadrant) and R0 (Ratio) Based on y and X Values247
Table 10-6. the Condition of UDRF and OVRF Flag in Mode 6247
Mode 7 Description248
Mode 8 Description248
Software Guideline248
Table 10-7. the Condition of UDRF and OVRF Flag in Mode 7248
Figure 10-3. TMU Program Guidline249
TMU Register250
Input Data0 Register (TMU_IDATA0)250
Input Data1 Register (TMU_IDATA1)250
Control Register (TMU_CTL)251
Data0 Register (TMU_DATA0)252
Data1 Register (TMU_DATA1)252
Status Register (TMU_STAT)252
Direct Memory Access Controller (DMA)254
Overview254
Characteristics254
Block Diagram255
Function Overview255
DMA Operation255
Figure 11-1. Block Diagram of DMA255
Table 11-1. DMA Transfer Operation256
Peripheral Handshake257
Arbitration257
Figure 11-2. Handshake Mechanism257
Address Generation258
Circular Mode258
Memory to Memory Mode258
Channel Configuration258
Interrupt259
DMA Request Mapping259
Figure 11-3. DMA Interrupt Logic259
Table 11-2. Interrupt Events259
Figure 11-4. DMA0 Request Mapping260
Table 11-3. DMA0 Requests for each Channel260
Table 11-4. DMA1 Requests for each Channel260
Figure 11-5. DMA1 Request Mapping261
Register Definition263
Interrupt Flag Register (DMA_INTF)263
Interrupt Flag Clear Register (DMA_INTC)264
Channel X Control Register (Dma_Chxctl)264
Channel X Counter Register (Dma_Chxcnt)266
Channel X Peripheral Base Address Register (Dma_Chxpaddr)267
Channel X Memory Base Address Register (Dma_Chxmaddr)267
Debug (DBG)269
Introduction269
JTAG/SW Function Description269
Switch JTAG or SW Interface269
Pin Assignment269
JTAG Daisy Chained Structure270
Debug Reset270
JEDEC-106 ID Code270
Debug Hold Function Description270
Debug Support for Power Saving Mode270
Debug Support for TIMER, I2C, WWDGT, FWDGT and CAN271
DBG Registers272
ID Code Register (DBG_ID)272
Control Register (DBG_CTL)272
Analog-To-Digital Converter (ADC)276
Introduction276
Characteristics276
Pins and Internal Signals277
Figure 13-1. ADC Module Block Diagram (for ADC0 and ADC1)277
Table 13-1. ADC Internal Input Signals277
Table 13-2. ADC Input Pins Definition277
Functional Overview278
Foreground Calibration Function279
Figure 13-2. ADC Module Block Diagram (for ADC2)279
ADC Clock280
ADCON Enable280
Single-Ended and Differential Input Channels280
Routine Sequence281
Operation Modes281
Figure 13-3. Single Operation Mode281
Figure 13-4. Continuous Operation Mode282
Figure 13-5. Scan Operation Mode, Continuous Operation Mode Disable283
Figure 13-6. Scan Operation Mode, Continuous Operation Mode Enable283
Figure 13-7. Discontinuous Operation Mode283
Conversion Result Threshold Monitor284
Data Storage Mode284
Figure 13-8. 12-Bit Data Storage Mode284
Sample Time Configuration285
External Trigger Configuration285
Figure 13-9. 6-Bit Data Storage Mode285
Table 13-3. External Trigger Source for ADC0 and ADC1285
Table 13-4. External Trigger Source for ADC2285
DMA Request286
ADC Internal Channels286
Programmable Resolution (DRES)287
On-Chip Hardware Oversampling287
Table 13-5. Tconv Timings Depending on Resolution287
Figure 13-10. 20-Bit to 16-Bit Result Truncation288
Figure 13-11. Numerical Example with 5-Bits Shift and Rounding288
Table 13-6. Maximum Output Results for N and M Combimations288
ADC Sync Mode289
Table 13-7. ADC Sync Mode Table289
Free Mode290
Routine Parallel Mode290
Figure 13-12. ADC Sync Block Diagram290
Routine Follow-Up Fast Mode291
Routine Follow-Up Slow Mode291
Figure 13-13. Routine Parallel Mode on 10 Channels291
Figure 13-14. Routine Follow-Up Fast Mode on Routine Sequence (the CTN Bit of the Adcs Are Set)291
ADC Interrupts292
Figure 13-15. Routine Follow-Up Slow Mode on Routine Sequence Channel292
ADC Registers293
Status Register (ADC_STAT)293
Control Register 0 (ADC_CTL0)294
Control Register 1 (ADC_CTL1)296
Sample Time Register 0 (ADC_SAMPT0)298
Sample Time Register 1 (ADC_SAMPT1)299
Watchdog High Threshold Register 0 (ADC_WDHT0)300
Watchdog Low Threshold Register 0 (ADC_WDLT0)300
Routine Sequence Register 0 (ADC_RSQ0)300
Routine Sequence Register 1 (ADC_RSQ1)301
Routine Sequence Register 2 (ADC_RSQ2)302
Routine Data Register (ADC_RDATA)302
Oversample Control Register (ADC_OVSAMPCTL)303
Watchdog 1 Channel Selection Register (ADC_WD1SR)304
Watchdog 2 Channel Selection Register (ADC_WD2SR)305
Watchdog Threshold Register 1 (ADC_WDT1)305
Watchdog Threshold Register 2 (ADC_WDT2)306
Differential Mode Control Register (ADC_DIFCTL)307
Digital-To-Analog Converter (DAC)308
Introduction308
Main Features308
Function Description309
DAC Enable309
DAC Output Buffer309
Figure 14-1. DAC Block Diagram309
Table 14-1. DAC I/O Description309
DAC Data Configuration310
DAC Trigger310
DAC Workflow310
Table 14-2. External Triggers of DAC310
DAC Output FIFO311
DAC Noise Wave311
DAC Output Calculate312
DMA Funtion312
Figure 14-2. DAC LFSR Algorithm312
Figure 14-3. DAC Triangle Noise Wave312
DAC Concurrent Conversion313
DAC Registers314
Control Register 0 (DAC_CTL0)314
Software Trigger Register (DAC_SWT)317
DAC_OUT0 12-Bit Right-Aligned Data Holding Register (OUT0_R12DH)317
DAC_OUT0 12-Bit Left-Aligned Data Holding Register (OUT0_L12DH)318
DAC_OUT0 8-Bit Right-Aligned Data Holding Register (OUT0_R8DH)318
DAC_OUT1 12-Bit Right-Aligned Data Holding Register (OUT1_R12DH)319
DAC_OUT1 12-Bit Left-Aligned Data Holding Register (OUT1_L12DH)319
DAC_OUT1 8-Bit Right-Aligned Data Holding Register (OUT1_R8DH)320
DAC Concurrent Mode 12-Bit Right-Aligned Data Holding Register (DACC_R12DH)320
DAC Concurrent Mode 12-Bit Left-Aligned Data Holding Register (DACC_L12DH)321
DAC Concurrent Mode 8-Bit Right-Aligned Data Holding Register (DACC_R8DH)321
DAC_OUT0 Data Output Register (OUT0_DO)322
DAC_OUT1 Data Output Register (OUT1_DO)322
DAC Status Register 0 (DAC_STAT0)323
DAC Control Register 1 (DAC_CTL1)323
DAC Status Register 1 (DAC_STAT1)324
Comparator (CMP)326
Overview326
Characteristic326
Function Overview326
CMP I/O Configuration327
Figure 15-1. CMP Block Diagram of Gd32E50X Series327
Table 15-1. CMP Inputs and Outputs Summary327
CMP Output Blanking328
CMP Register Write Protection329
Figure 15-2. the CMP Outputs Signal Blanking329
CMP Registers330
CMP1 Control/Status Register (CMP1_CS)330
CMP3 Control/Status Register (CMP3_CS)331
CMP5 Control/Status Register (CMP5_CS)333
Watchdog Timer (WDGT)336
Free Watchdog Timer (FWDGT)336
Overview336
Characteristics336
Function Overview336
Figure 16-1. Free Watchdog Block Diagram337
Table 16-1. Min/Max FWDGT Timeout Period at 40 Khz (IRC40K)337
Register Definition339
Window Watchdog Timer (WWDGT)342
Overview342
Characteristics342
Function Overview342
Figure 16-2. Window Watchdog Timer Block Diagram342
Figure 16-3. Window Watchdog Timing Diagram343
Table 16-2. Min/Max Timeout Value at 100 Mhz (F PCLK1 )344
Register Definition345
Real-Time Clock (RTC)347
Overview347
Characteristics347
Function Overview347
RTC Reset348
RTC Reading348
RTC Configuration348
Figure 17-1. Block Diagram of RTC348
RTC Flag Assertion349
Figure 17-2. RTC Second and Alarm Waveform Example (RTC_PSC = 3, RTC_ALRM = 2)349
Figure 17-3. RTC Second and Overflow Waveform Example (RTC_PSC= 3)350
RTC Register351
RTC Interrupt Enable Register (RTC_INTEN)351
RTC Control Register (RTC_CTL)351
RTC Prescaler High Register (RTC_PSCH)352
RTC Prescaler Low Register (RTC_PSCL)353
RTC Divider High Register (RTC_DIVH)353
RTC Divider Low Register (RTC_DIVL)353
RTC Counter High Register (RTC_CNTH)354
RTC Counter Low Register (RTC_CNTL)354
RTC Alarm High Register (RTC_ALRMH)355
RTC Alarm Low Register (RTC_ALRML)355
Timer (Timerx)356
Table 18-1. Timers (Timerx) Are Divided into Five Sorts356
Advanced Timer (Timerx, X=0, 7)357
Overview357
Characteristics357
Block Diagram358
Function Overview358
Figure 18-1. Advanced Timer Block Diagram358
Figure 18-2. Timing Chart of Internal Clock Divided by 1359
Figure 18-3. Timing Chart of PSC Value Change from 0 to 2360
Figure 18-4. Timing Chart of up Counting Mode, PSC=0/2360
Figure 18-5. Timing Chart of up Counting Mode, Change Timerx_Car Ongoing361
Figure 18-6. Timing Chart of down Counting Mode, PSC=0/2362
Figure 18-7. Timing Chart of down Counting Mode, Change Timerx_Car Ongoing363
Figure 18-8. Timing Chart of Center-Aligned Counting Mode364
Figure 18-9. Repetition Timechart for Center-Aligned Counter365
Figure 18-10. Repetition Timechart for Up-Counter365
Figure 18-11. Repetition Timechart for Down-Counter366
Figure 18-12. Channel Input Capture Principle367
Figure 18-13. Channel Output Compare Principle (with Complementary Output, X=0,1,2)368
Figure 18-14. Channel Output Compare Principle (CH3_O)368
Figure 18-15. Output-Compare in Three Modes369
Figure 18-16. Timing Chart of EAPWM371
Figure 18-17. Timing Chart of CAPWM371
Table 18-2. Complementary Outputs Controlled by Parameters373
Figure 18-18. Complementary Output with Dead-Time Insertion374
Figure 18-19. Output Behavior of the Channel in Response to a Break (the Break High Active)375
Figure 18-20. Counter Behavior with CI0FE0 Polarity Non-Inverted in Mode 2376
Figure 18-21. Counter Behavior with CI0FE0 Polarity Inverted in Mode 2376
Table 18-3. Counting Direction in Different Quadrature Decoder Mode376
Figure 18-22. Hall Sensor I S Used to BLDC Motor377
Figure 18-23. Hall Sensor Timing between Two Timers378
Table 18-4. Examples of Slave Mode378
Figure 18-24. Restart Mode379
Figure 18-25. Pause Mode380
Figure 18-26. Event Mode380
Figure 18-27. Single Pulse Mode, Timerx_Chxcv = 4, Timerx_Car=99381
Figure 18-28. Timer0 Master/Slave Mode Example381
Figure 18-29. Trigger TIMER0 and TIMER2 by the CI0 Signal of TIMER2383
Timerx Registers(X=0, 7)385
General Level0 Timer (Timerx, X=1, 2, 3, 4)413
Overview413
Characteristics413
Block Diagram413
Figure 18-30. General Level 0 Timer Block Diagram413
Function Overview414
Figure 18-31. Timing Chart of Internal Clock Divided by 1415
Figure 18-32. Timing Chart of PSC Value Change from 0 to 2416
Figure 18-33. Timing Chart of up Counting Mode, PSC=0/2417
Figure 18-34. Timing Chart of up Counting Mode, Change Timerx_Car Ongoing417
Figure 18-35. Timing Chart of down Counting Mode,Psc=0/2418
Figure 18-36. Timing Chart of down Counting Mode, Change Timerx_Car Ongoing419
Figure 18-37. Timing Chart of Center-Aligned Counting Mode420
Figure 18-38. Channel Input Capture Principle421
Figure 18-39. Channel Output Compare Principle (X=0,1,2,3)422
Figure 18-40. Output-Compare in Three Modes423
Figure 18-41. Timing Chart of EAPWM424
Figure 18-42. Timing Chart of CAPWM425
Table 18-5. Examples of Slave Mode426
Figure 18-43. Restart Mode427
Figure 18-44. Pause Mode427
Figure 18-45. Event Mode428
Timerx Registers(X=1, 2, 3, 4)429
General Level1 Timer (Timerx, X=8, 11)455
Overview455
Characteristics455
Block Diagram455
Figure 18-46. General Level1 Timer Block Diagram455
Function Overview456
Figure 18-47. Timing Chart of Internal Clock Divided by 1457
Figure 18-48. Timing Chart of PSC Value Change from 0 to 2458
Figure 18-49. Timing Chart of up Counting Mode, PSC=0/2458
Figure 18-50. Timing Chart of up Counting Mode, Change Timerx_Car Ongoing459
Figure 18-51. Channel Input Capture Principle460
Figure 18-52. Channel Output Compare Principle (X=0,1)461
Figure 18-53. Output-Compare under Three Modes462
Figure 18-54. PWM Mode Timechart463
Figure 18-55. Restart Mode464
Table 18-6. Examples of Slave Mode464
Figure 18-56. Pause Mode465
Figure 18-57. Event Mode465
Figure 18-58. Single Pulse Mode Timerx_Chxcv = 4 Timerx_Car=99466
Timerx Registers(X=8, 11)467
General Level2 Timer (Timerx, X=9, 10, 12, 13)480
Overview480
Characteristics480
Block Diagram480
Figure 18-59. General Level2 Timer Block Diagram480
Function Overview481
Figure 18-60. Timing Chart of Internal Clock Divided by 1482
Figure 18-61. Timing Chart of PSC Value Change from 0 to 2482
Figure 18-62. Timing Chart of up Counting Mode, PSC=0/2483
Figure 18-63. Timing Chart of up Counting Mode, Change Timerx_Car Ongoing484
Figure 18-64. Channel Input Capture Principle485
Figure 18-65. Channel Output Compare Principle486
Figure 18-66. Output-Compare under Three Modes487
Timerx Registers(X=9, 10, 12, 13)489
Basic Timer (Timerx, X=5, 6)500
Overview500
Characteristics500
Block Diagram500
Function Overview500
Figure 18-67. Basic Timer Block Diagram500
Figure 18-68. Timing Chart of Internal Clock Divided by 1501
Figure 18-69. Timing Chart of PSC Value Change from 0 to 2501
Figure 18-70. Timing Chart of up Counting Mode, PSC=0/2502
Figure 18-71. Timing Chart of up Counting Mode, Change Timerx_Car Ongoing503
Timerx Registers(X=5, 6)504
Super High-Resolution Timer (SHRTIMER)509
Overview509
Characteristics509
Block Diagram509
Figure 19-1. SHRTIMER Block Diagram509
Function Overview510
Master_Timer Unit510
Figure 19-2. Master_Timer Diagram510
Table 19-1. the Limitations of Auto-Reload and Compare y (Y=0..3) Register511
Figure 19-3. Counter Clock When Divided by 32512
Table 19-2. Resolution with F512
Figure 19-4. Counter Behavior in Single Pulse Mode513
Figure 19-5. Counter Behavior in Continuous Mode513
Figure 19-6. Repetition Counter Behavior in Continuous Mode514
Figure 19-7. Repetition Counter Behavior in Single Pulse Mode with CNTRSTM = 0514
Figure 19-8. Repetition Counter Behavior in Single Pulse Mode with CNTRSTM = 1515
Figure 19-9 Reset Event Resynchronization When Prescaling Ratio Is 128515
Table 19-3. Master_Timer Shadow Registers and Update Event516
Slave_Timerx(X=0518
Figure 19-10. Slave_Timerx Diagram518
Table 19-4. the Limitations of Counter and Capture y(Y=0,1) Value Registers519
Figure 19-11. Capture 0 Triggered by EXEV0 and EXEV1522
Figure 19-12．Compare 1 Behavior with Stxcar=0X8, Stxcmp1V=0X02523
Figure 19-13. Compare Delayed Mode Chart523
Figure 19-14. Compare 1 Delayed Mode 0524
Figure 19-15. Compare 1 Delayed Mode 1525
Figure 19-16. Compare Delayed Mode with SHWEN = 0526
Figure 19-17. Channel Output Diagram526
Figure 19-18. O0PRE Wave: Set on CMP0, Reset on CMP1527
Table 19-5. Slave_Timer Interconnection Event528
Figure 19-19. Arbitration Mechanism During each T529
Figure 19-20． Arbitration Mechanism Example530
Figure 19-23. Super High-Resolution Oxpre Wave531
Figure 19-24. Oxpre Wave with CNTCKDIV[3:0] = 4'B0110532
Figure 19-25. C0OPRE Wave in Regular Mode532
Figure 19-26. C0OPRE and C1OPRE Complementary Wave with de Ad-Time534
Figure 19-27. Complementary Wave with Pulse Width Less than Dead-Time534
Figure 19-28. Structure Chart in Balanced Mode535
Figure 19-29. C0OPRE and C1OPRE Wave in Balanced Mode536
Table 19-6. Crossbar and IDLE Control Stage Work Together537
Table 19-7. Request to Enter in IDLE and Exit IDLE State538
Figure 19-30. ISO0 = 0 and CHOP = 0 in Delayed IDLE539
Figure 19-31. ISO0 = 1 and CHOP = 0 in Delayed IDLE539
Figure 19-32. ISO0 = 0 and CHOP = 1 in Delayed IDLE540
Figure 19-33. ISO0 = 1 and CHOP = 1 in Delayed IDLE540
Figure 19-34. Balanced IDEL with ISO0 = 0 and ISO1 = 0541
Table 19-8. Output During IDEL State Controlled by Bunch Mode542
Figure 19-35. Stxchy_O Wave with Chyp=0 or Chyp=1543
Table 19-9. Output Stage Status Programming (X=0543
Figure 19-36. Carrier-Signal Structure Diagram544
Figure 19-37. SHRTIMER Output with Carrier-Signal Mode Enabled545
Table 19-10. Slave_Timerx Shadow Registers and Update Event546
Table 19-11. Stxupiny(Y=0..2) and Chip Internal Signal546
Figure 19-38. Blanking Mode and Windowing Mode547
Table 19-12. Filtering Signals Mapping in Blanking Mode547
Table 19-13. Filtering Signals Mapping in Windowing Mode548
DLL Calibrate549
Bunch Mode549
Figure 19-39. Bunch Mode Timing Chart550
Table 19-14. Chip Internal Signal in Bunch Mode550
Figure 19-40. Regular Entry for Bunch Mode551
Figure 19-41. Delayed Entry for Bunch Mode553
Synchronization Input/Output554
Figure 19-42. Emulate Bunch Mode Example554
External Event555
Figure 19-43. Extern Event y(Y=0..4) Processed Diagram556
Figure 19-44. Extern Event y(Y=5..9) Processed Diagram556
Fault Input557
Figure 19-45. Fault Input Diagram557
Table 19-15. External Events Mapping557
Table 19-16. Fault Channel Mapping558
Trigger to ADC559
Trigger to DAC560
Figure 19-46. Trigger to ADC Selection Overview560
Figure 19-47. Trigger to DAC Selection Overview560
Interrupt561
Table 19-17. Interrupt Mapping561
DMA Request562
Table 19-18. DMA Request Mapping562
DMA Mode563
Debug Mode564
Register Definition564
Figure 19-48. DMA Mode Operation Flowchart564
Master_Timer Registers565
Slave_Timerx Registers(X=0577
Common Registers639
Universal Synchronous/Asynchronous Receiver /Transmitter (USART)683
Table 20-1. Description of USART Important Pins684
Figure 20-1. USART Module Block Diagram685
Figure 20-2. USART Character Frame (8 Bits Data and 1 Stop Bit)685
Table 20-2. Configuration of Stop Bits685
Figure 20-3. USART Transmit Procedure687
Figure 20-4. Receiving a Frame Bit by Oversampling Method688
Figure 20-5. Configuration Step When Using DMA for USART Transmission690
Figure 20-6. Configuration Steps When Using DMA for USART Reception691
Figure 20-7. Hardware Flow Control between Two Usarts691
Figure 20-8. Hardware Flow Control692
Figure 20-9. Break Frame Occurs During Idle State693
Figure 20-10. Break Frame Occurs During a Frame693
Figure 20-11. Example of USART in Synchronous Mode694
Figure 20-12. 8-Bit Format USART Synchronous Waveform (CLEN=1)694
Figure 20-13. Irda SIR ENDEC Module695
Figure 20-14. Irda Data Modulation695
Figure 20-15. ISO7816-3 Frame Format696
Table 20-3. USART Interrupt Requests698
Figure 20-16. USART Interrupt Mapping Diagram699
Table 20-4. Description of USART Important Pins715
Figure 20-17. USART Module Block Diagram716
Figure 20-18. USART Character Frame (8 Bits Data and 1 Stop Bit)716
Table 20-5. Configuration of Stop Bits716
Figure 20-19. USART Transmit Procedure718
Figure 20-20. Oversampling Method of a Receive Frame Bit (OSB=0)719
Figure 20-21. Configuration Step When Using DMA for USART Transmission721
Figure 20-22. Configuration Step When Using DMA for USART Reception722
Figure 20-23. Break Frame Occurs During Idle State723
Figure 20-24. Break Frame Occurs During a Frame723
Figure 20-25. Example of USART in Synchronous Mode724
Figure 20-26. 8-Bit Format USART Synchronous Waveform (CLEN=1)724
Figure 20-27. Irda SIR ENDEC Module725
Figure 20-28. Irda Data Modulation725
Figure 20-29. ISO7816-3 Frame Format726
Figure 20-30. USART Receive FIFO Structure729
Table 20-6. USART Interrupt Requests729
Figure 20-31. USART Interrupt Mapping Diagram731
Figure 21-1. I2C Module Block Diagram749
Table 21-1. Definition of I2C-Bus Terminology750
Figure 21-2. Data Validation751
Figure 21-3. START and STOP Signal751
Figure 21-4. Clock Synchronization752
Figure 21-5. SDA Line Arbitration752
Figure 21-6. I2C Communication Flow with 7-Bit Address753
Figure 21-7. I2C Communication Flow with 10-Bit Address (Master Transmit)753
Figure 21-8. I2C Communication Flow with 10-Bit Address (Master Receive)753
Figure 21-9. Programming Model for Slave Transmitting (10-Bit Address Mode)755
Figure 21-10. Programming Model for Slave Receiving (10-Bit Address Mode)755
Figure 21-11. Programming Model for Master Transmitting (10-Bit Address Mode)757
Figure 21-12. Programming Model for Master Receiving Using Solution a759
Figure 21-13. Programming Model for Master Receiving Mode Using Solution B (10-Bit Address Mode)760
Table 21-2. Event Status Flags764
Table 21-3. Error Flags765
Figure 21-14. I2C Module Block Diagram780
Table 21-4. Definition of I2C-Bus Terminology (Refer to the I2C Specification of Philips Semiconductors)781
Figure 21-15. Data Validation782
Figure 21-16. START and STOP Signal783
Figure 21-17. I2C Communication Flow with 10-Bit Address (Master Transmit)783
Figure 21-18. I2C Communication Flow with 7-Bit Address (Master Transmit)784
Figure 21-19. I2C Communication Flow with 7-Bit Address (Master Receive)784
Figure 21-20. I2C Communication Flow with 10-Bit Address (Master Receive When HEAD10R=0)784
Figure 21-21. I2C Communication Flow with 10-Bit Address (Master Receive When HEAD10R=1)784
Figure 21-22. Data Hold Time785
Figure 21-23. Data Setup Time785
Table 21-5. Data Setup Time and Data Hold Time786
Figure 21-24. Data Transmission787
Figure 21-25. Data Reception788
Table 21-6. Communication Modes to be Shut down788
Figure 21-26. I2C Initialization in Slave Mode791
Figure 21-27. Programming Model for Slave Transmitting When SS=0792
Figure 21-28. Programming Model for Slave Transmitting When SS=1793
Figure 21-29. Programming Model for Slave Receiving794
Figure 21-30. I2C Initialization in Master Mode795
Figure 21-31. Programming Model for Master Transmitting (N<=255)796
Figure 21-32. Programming Model for Master Transmitting (N>255)797
Figure 21-33. Programming Model for Master Receiving (N<=255)798
Figure 21-34. Programming Model for Master Receiving (N>255)799
Figure 21-35. Smbus Master Transmitter and Slave Receiver Communication Flow802
Figure 21-36. Smbus Master Receiver and Slave Transmitter Communication Flow803
Table 21-7. I2C Error Flags804
Table 21-8. I2C Interrupt Events804
Figure 22-1. Block Diagram of SPI821
Table 22-1. SPI Signal Description821
Table 22-2. Quad-SPI Signal Description822
Figure 22-2. SPI Timing Diagram in Normal Mode823
Figure 22-3. SPI Timing Diagram in Quad-SPI Mode (CKPL=1, CKPH=1, LF=0)823
Table 22-3. NSS Function in Slave Mode824
Table 22-4. NSS Function in Master Mode824
Table 22-5. SPI Operation Modes825
Figure 22-4. a Typical Full-Duplex Connection826
Figure 22-5. a Typical Simplex Connection (Master: Receive, Slave: Transmit)826
Figure 22-6. a Typical Simplex Connection (Master: Transmit Only, Slave: Receive)827
Figure 22-7. a Typical Bidirectional Connection827
Figure 22-8. Timing Diagram of TI Master Mode with Discontinuous Transfer829
Figure 22-9. Timing Diagram of TI Master Mode with Continuous Transfer829
Figure 22-10. Timing Diagram of TI Slave Mode829
Figure 22-11. Timing Diagram of NSS Pulse with Continuous Transmit830
Figure 22-12. Timing Diagram of Write Operation in Quad-SPI Mode831
Figure 22-13. Timing Diagram of Read Operation in Quad-SPI Mode832
Figure 22-14. Block Diagram of I2S835
Table 22-6. SPI Interrupt Requests835
Figure 22-15. I2S Phillips Standard Timing Diagram (DTLEN=00, CHLEN=0, CKPL=0)836
Figure 22-16. I2S Phillips Standard Timing Diagram (DTLEN=00, CHLEN=0, CKPL=1)837
Figure 22-17. I2S Phillips Standard Timing Diagram (DTLEN=10, CHLEN=1, CKPL=0)837
Figure 22-18. I2S Phillips Standard Timing Diagram (DTLEN=10, CHLEN=1, CKPL=1)837
Figure 22-19. I2S Phillips Standard Timing Diagram (DTLEN=01, CHLEN=1, CKPL=0)837
Figure 22-20. I2S Phillips Standard Timing Diagram (DTLEN=01, CHLEN=1, CKPL=1)837
Figure 22-21. I2S Phillips Standard Timing Diagram (DTLEN=00, CHLEN=1, CKPL=0)838
Figure 22-22. I2S Phillips Standard Timing Diagram (DTLEN=00, CHLEN=1, CKPL=1)838
Figure 22-23. MSB Justified Standard Timing Diagram (DTLEN=00, CHLEN=0, CKPL=0)838
Figure 22-24. MSB Justified Standard Timing Diagram (DTLEN=00, CHLEN=0, CKPL=1)838
Figure 22-25. MSB Justified Standard Timing Diagram (DTLEN=10, CHLEN=1, CKPL=0)839
Figure 22-26. MSB Justified Standard Timing Diagram (DTLEN=10, CHLEN=1, CKPL=1)839
Figure 22-27. MSB Justified Standard Timing Diagram (DTLEN=01, CHLEN=1, CKPL=0)839
Figure 22-28. MSB Justified Standard Timing Diagram (DTLEN=01, CHLEN=1, CKPL=1)839
Figure 22-29. MSB Justified Standard Timing Diagram (DTLEN=00, CHLEN=1, CKPL=0)839
Figure 22-30. MSB Justified Standard Timing Diagram (DTLEN=00, CHLEN=1, CKPL=1)839
Figure 22-31. LSB Justified Standard Timing Diagram (DTLEN=01, CHLEN=1, CKPL=0)840
Figure 22-32. LSB Justified Standard Timing Diagram (DTLEN=01, CHLEN=1, CKPL=1)840
Figure 22-33. LSB Justified Standard Timing Diagram (DTLEN=00, CHLEN=1, CKPL=0)840
Figure 22-34. LSB Justified Standard Timing Diagram (DTLEN=00, CHLEN=1, CKPL=1)840
Figure 22-35. PCM Standard Short Frame Synchronization Mode Timing Diagram (DTLEN=00, CHLEN=0, CKPL=0)841
Figure 22-36. PCM Standard Short Frame Synchronization Mode Timing Diagram (DTLEN=00, CHLEN=0, CKPL=1)841
Figure 22-37. PCM Standard Short Frame Synchronization Mode Timing Diagram (DTLEN=10, CHLEN=1, CKPL=0)841
Figure 22-38. PCM Standard Short Frame Synchronization Mode Timing Diagram (DTLEN=10, CHLEN=1, CKPL=1)841
Figure 22-39. PCM Standard Short Frame Synchronization Mode Timing Diagram841
Figure22-40. PCM Standard Short Frame Synchronization Mode Timing Diagram (DTLEN=01, CHLEN=1, CKPL=1)842
Figure 22-41. PCM Standard Short Frame Synchronization Mode Timing Diagram (DTLEN=00, CHLEN=1, CKPL=0)842
Figure 22-42. PCM Standard Short Frame Synchronization Mode Timing Diagram (DTLEN=00, CHLEN=1, CKPL=1)842
Figure 22-43. PCM Standard Long Frame Synchronization Mode Timing Diagram (DTLEN=00, CHLEN=0, CKPL=0)842
Figure22-44. PCM Standard Long Frame Synchronization Mode Timing Diagram842
Figure 22-45. PCM Standard Long Frame Synchronization Mode Timing Diagram (DTLEN=10, CHLEN=1, CKPL=0)843
Figure 22-46. PCM Standard Long Frame Synchronization Mode Timing Diagram843
Figure 22-47. PCM Standard Long Frame Synchronization Mode Timing Diagram (DTLEN=01, CHLEN=1, CKPL=0)843
Figure 22-48. PCM Standard Long Frame Synchronization Mode Timing Diagram (DTLEN=01, CHLEN=1, CKPL=1)843
Figure 22-49. PCM Standard Long Frame Synchronization Mode Timing Diagram (DTLEN=00, CHLEN=1, CKPL=0)843
Figure 22-50. PCM Standard Long Frame Synchronization Mode Timing Diagram (DTLEN=00, CHLEN=1, CKPL=1)844
Figure 22-51. Block Diagram of I2S Clock Generator844
Table 22-7. I2S Bitrate Calculation Formulas844
Table 22-8. Audio Sampling Frequency Calculation Formulas845
Table 22-9. Direction of I2S Interface Signals for each Operation Mode845
Figure 22-52. I2S Initialization Sequence846
Figure 22-53. I2S Master Reception Disabling Sequence848
Table 22-10. I2S Interrupt850
Table 23-1. SQPI Controller Mode Definition863
Figure 23-1. SQPI_PL Example864
Figure 23-2. SQPI_SC Example865
Figure 23-3. SQPI_RDID Example (SQPI_IDLEN=00)865
Figure 23-4. SQPI_CLK Example866
Figure 23-5. SQPI SSS Mode Timing (SPI)867
Figure 23-6. SQPI SSQ Mode Timing867
Figure 23-7. SQPI SQQ Mode Timing (SQPI)867
Figure 23-8. SQPI QQQ Mode Timing (QPI)868
Figure 23-9. SQPI SSD Mode Timing868
Figure 23-10. SQPI SDD Mode Timing868
Figure 24-1. SDIO "No Response" and "No Data" Operations874
Figure 24-2. SDIO Multiple Blocks Read Operation875
Figure 24-3. SDIO Multiple Blocks Write Operation875
Figure 24-4. SDIO Sequential Read Operation875
Figure 24-5. SDIO Sequential Write Operation876
Figure 24-6. SDIO Block Diagram876
Table 24-1. SDIO I/O Definitions877
Figure 24-7. Command Token Format883
Table 24-2. Command Format883
Table 24-3. Card Command Classes (Cccs)884
Table 24-4. Basic Commands (Class 0)886
Table 24-5. Block-Oriented Read Commands (Class 2)888
Table 24-6. Stream Read Commands (Class 1) and Stream Write Commands (Class 3)889
Table 24-7. Block-Oriented Write Commands (Class 4)889
Table 24-8. Erase Commands (Class 5)890
Table 24-9. Block Oriented Write Protection Commands (Class 6)891
Table 24-10. Lock Card (Class 7)891
Table 24-11. Application-Specific Commands (Class 8)892
Table 24-12. I/O Mode Commands (Class 9)893
Table 24-13. Switch Function Commands (Class 10)894
Figure 24-8. Response Token Format895
Table 24-14. Response R1895
Table 24-15. Response R2896
Table 24-16. Response R3896
Table 24-17. Response R4 for MMC896
Table 24-18. Response R4 for SD I/O897
Table 24-19. Response R5 for MMC897
Table 24-20. Response R5 for SD I/O897
Table 24-21. Response R6897
Figure 24-9. 1-Bit Data Bus Width898
Table 24-22. Response R7898
Figure 24-10. 4-Bit Data Bus Width899
Figure 24-11. 8-Bit Data Bus Width899
Table 24-23. Card Status900
Table 24-24. SD Status903
Table 24-25. Performance Move Field904
Table 24-26. AU_SIZE Field905
Table 24-27. Maximum au Size905
Table 24-28. Erase Size Field905
Table 24-29. Erase Timeout Field906
Table 24-30. Erase Offset Field906
Table 24-31. Lock Card Data Structure915
Figure 24-12. Read Wait Control by Stopping SDIO_CLK917
Figure 24-13. Read Wait Operation Using SDIO_DAT[2]917
Figure 24-14. Function2 Read Cycle Inserted During Function1 Multiple Read Cycle918
Figure 24-15. Read Interrupt Cycle Timing919
Figure 24-16. Write Interrupt Cycle Timing919
Figure 24-17. Multiple Block 4-Bit Read Interrupt Cycle Timing920
Figure 24-18. Multiple Block 4-Bit Write Interrupt Cycle Timing920
Figure 24-19. the Operation for Command Completion Disable Signal921
Table 24-32. Sdio_Respx Register at Different Response Type926
Figure 25-1. the EXMC Block Diagram937
Figure 25-2. EXMC Memory Banks938
Figure 25-3. Four Regions of Bank0 Address Mapping938
Figure 25-4. NAND/PC Card Address Mapping940
Figure 25-5. Diagram of Bank1 Common Space940
Table 25-1. nor Flash Interface Signals Description941
Table 25-2. PSRAM Non-Muxed Signal Description942
Table 25-3. EXMC Bank 0 Supports All Transactions942
Table 25-4. nor / PSRAM Controller Timing Parameters943
Table 25-5. Exmc_Timing Models944
Figure 25-6. Mode 1 Read Access945
Figure 25-7. Mode 1 Write Access945
Table 25-6. Mode 1 Related Registers Configuration945
Figure 25-8. Mode a Read Access946
Figure 25-9. Mode a Write Access947
Table 25-7. Mode a Related Registers Configuration947
Figure 25-10. Mode 2/B Read Access948
Figure 25-11. Mode 2 Write Access949
Figure 25-12. Mode B Write Access949
Table 25-8. Mode 2/B Related Registers Configuration949
Figure 25-13. Mode C Read Access950
Figure 25-14. Mode C Write Access951
Table 25-9. Mode C Related Registers Configuration951
Figure 25-15. Mode D Read Access952
Figure 25-16. Mode D Write Access953
Table 25-10. Mode D Related Registers Configuration953
Figure 25-17. Multiplex Mode Read Access954
Figure 25-18. Multiplex Mode Write Access954
Table 25-11. Multiplex Mode Related Registers Configuration955
Figure 25-19. Read Access Timing Diagram under Async-Wait Signal Assertion956
Figure 25-20. Write Access Timing Diagram under Async-Wait Signal Assertion956
Figure 25-21. Read Timing of Synchronous Multiplexed Burst Mode958
Table 25-12. Timing Configurations of Synchronous Multiplexed Read Mode958
Figure 25-22. Write Timing of Synchronous Multiplexed Burst Mode959
Table 25-13. Timing Configurations of Synchronous Multiplexed Write Mode959
Table 25-14. 8-Bit or 16-Bit NAND Interface Signal960
Table 25-15. 16-Bit PC Card Interface Signal961
Table 25-16. Bank1/2/3 of EXMC Support the Memory and Access Mode961
Figure 25-23. Access Timing of Common Memory Space of PC Card Controller962
Table 25-17. NAND Flash or PC Card Programmable Parameters962
Figure 25-24. Access to None "NCE Don't Care" NAND Flash963
Figure 26-1. CAN Module Block Diagram978
Figure 26-2. Transmission Register980
Figure 26-3. State of Transmit Mailbox981
Figure 26-4. Reception Register983
Figure 26-5. 32-Bit Filter984
Figure 26-6. 16-Bit Filter984
Figure 26-7. 32-Bit Mask Mode Filter984
Figure 26-8. 16-Bit Mask Mode Filter985
Figure 26-9. 32-Bit List Mode Filter985
Figure 26-10. 16-Bit List Mode Filter985
Table 26-1. 32-Bit Filter Number985
Table 26-2. Filtering Index986
Figure 26-11. the Bit Time988
Figure 26-12. Transmitter Delay Measurement991
Table 26-3. CAN Event / Interrupt Flags993
Figure 27-1. ENET Module Block Diagram1019
Figure 27-2. MAC / Tagged MAC Frame Format1020
Table 27-1. Ethernet Signals (MII Default)1021
Table 27-2. Ethernet Signals (MII Remap)1021
Table 27-3. Ethernet Signals (RMII Default)1022
Table 27-4. Ethernet Signals (RMII Remap)1022
Figure 27-3. Station Management Interface Signals1023
Figure 27-4. Media Independent Interface Signals1024
Table 27-5. Clock Range1024
Figure 27-5. Reduced Media-Independent Interface Signals1026
Table 27-6. Rx Interface Signal Encoding1026
Table 27-7. Destination Address Filtering Table1031
Table 27-8. Source Address Filtering Table1032
Figure 27-6. Descriptor Ring and Chain Structure1039
Figure 27-7. Transmit Descriptor in Normal Mode1044
Figure 27-8. Transmit Descriptor in Enhanced Mode1050
Figure 27-9. Receive Descriptor in Normal Mode1054
Table 27-9. Error Status Decoding in Receive Descriptor0, Only Used for Normal Descriptor1057
Figure 27-10. Receive Descriptor in Enhanced Mode1060
Figure 27-11. Wakeup Frame Filter Register1065
Figure 27-12. System Time Update Using the Fine Correction Method1067
Figure 27-13. MAC Interrupt Scheme1072
Figure 27-14. Ethernet Interrupt Scheme1073
Figure 27-15. Wakeup Frame Filter Register1083
Table 27-10. Supported Time Stamp Snapshot with PTP Register Configuration1102
Figure 28-1. USBD Block Diagram1125
Table 28-1. USBD Signal Description1125
Figure 28-2. an Example with Buffer Descriptor Table Usage (USBD_BADDR = 0)1127
Table 28-2. Double-Buffering Buffer Flag Definition1128
Table 28-3. Double Buffer Usage1128
Table 28-4. Reception Status Encoding1140
Table 28-5. Endpoint Type Encoding1140
Table 28-6. Endpoint Kind Meaning1140
Table 28-7. Transmission Status Encoding1141
Figure 29-1. USBHS Block Diagram1145
Table 29-1. USBHS Signal Description1145
Table 29-2. USBHS Supported Speeds1146
Figure 29-2. Connection Using Internal Embedded PHY with Host or Device Mode1147
Figure 29-3. Connection Using Internal Embedded PHY with OTG Mode1148
Figure 29-4. Connection Using External ULPI PHY1148
Figure 29-5. State Transition Diagram of Host Port1149
Figure 29-6. Host Mode FIFO Space in SRAM1155
Figure 29-7. Host Mode FIFO Access Register Map1155
Figure 29-8. Device Mode FIFO Space in SRAM1156
Figure 29-9. Device Mode FIFO Access Register Map1157
Table 29-3. USBHS Global Interrupt1165
Table 30-1. List of Abbreviations Used in Register1241
Table 30-2. List of Terms1241
Table 31-1. Revision History1243

Operating Temperature	-40°C to +85°C
Flash Memory	Up to 512 KB
SRAM	Up to 128 KB
DAC	Up to 2 x 12-bit DACs
Communication Interfaces	USART, UART, SPI, I2C, I2S, USB, CAN
Package Types	LQFP
Timers	Advanced, General-purpose, Basic

GigaDevice Semiconductor GD32E50 Series User Manual

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GigaDevice Semiconductor GD32E50 Series Specifications

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