GigaDevice Semiconductor GD32E50 Series - CMP3 Control;Status Register (CMP3_CS)

GD32E50x User Manual
331
17:16
Reserved
Must be kept at reset value.
15
CMP1PL
Polarity of CMP1 output
This bit is used to select the polarity of CMP1 output.
0 : Output is not inverted
1 : Output is inverted
14
Reserved
Must be kept at reset value
13:10
CMP1OSEL[3:0]
Comparator 1 output selection
These bits are used to select the destination of the CMP1 output.
0000: no selection
0001: TIMER0 break input
0010~0110: Reserved
0111: TIMER0 channel0 input capture
1000: TIMER1 channel3 input capture
1001: Reserved
1010: TIMER2 channel0 input capture
1011~1111: Reserved
9:7
Reserved
Must be kept at reset value
6:4
CMP1MSEL[2:0]
CMP1_IM input selection
These bits, together w ith bit 22, are used to select the source connected to the
CMP1_IM input of the CMP1.
0000: V
REFINT
/4
0001: V
REFINT
/2
0010: V
REFINT
*3/4
0011: V
REFINT
0100: PA4 (DAC_OUT0)
0101: PA5(DAC_OUT1)
0110: PA2
0111~1111: Reserved
3:1
Reserved
Must be kept at reset value
0
CMP1EN
CMP1 enable
0: CMP1 disabled
1: CMP1 enabled
15.4.2. CMP3 Control/status register (CMP3_CS)
Address offset: 0x28
Reset value: 0x0000 0000
This register has to be accessed by word (32-bit).