GigaDevice Semiconductor GD32E50 Series - Figure 11-5. DMA1 Request Mapping

GD32E50x User Manual
261
Peripheral
Channel 0
Channel 1
Channel 2
Channel 3
Channel 4
Channel 5
Channel 6
TIMER2
●
TIMER2_CH2
TIMER2_CH3
TIMER2_UP
●
●
TIMER2_CH0
TIMER2_TG
●
TIMER3
TIMER3_CH0
●
●
TIMER3_CH1
TIMER3_CH2
●
TIMER3_UP
ADC0
ADC0
●
●
●
●
●
●
SPI/I2S
●
SPI0_RX
SPI0_TX
SPI1/I2S1_RX
SPI1/I2S1_TX
I2S1ADD_RX
I2S1ADD_TX
USART
●
USART2_TX
USART2_RX
USART0_TX
USART0_RX
USART1_RX
USART1_TX
I2C
●
●
●
I2C1_TX
I2C2_TX
I2C1_RX
I2C2_RX
I2C0_TX
I2C0_RX
SHRTIMER
●
SHRTIMER_M
SHRTIMER_0
SHRTIMER_1
SHRTIMER_2
SHRTIMER_3
SHRTIMER_4
Figure 11-5. DMA1 request mapping
SPI2/I2S2_RX
TIMER4_CH3
TIMER4_TG
TIMER7_CH2
TIMER7_UP
or
or
Channel 0
M2M
Hardware
priority
high
low
SPI2/I2S2_TX
TIMER4_CH2
TIMER4_UP
TIMER7_CH3
TIMER7_TG
TIMER7_CMT
or
or
Channel 1
M2M
I2S2ADD_RX
UART3_RX
USART5_RX
TIMER5_UP
DAC_CH0
TIMER7_CH0
or
or
Channel 2
M2M
I2S2ADD_TX
SDIO
TIMER4_CH1
TIMER6_UP
DAC_CH1
or
or
Channel 3
M2M
ADC2
UART3_TX
USART5_TX
TIMER4_CH0
TIMER7_CH1
or
or
Channel 4
M2M
Table 11-4. DMA1 requests for each channel
Peripheral
Channel 0
Channel 1
Channel 2
Channel 3
Channel 4
TIMER4
TIMER4_CH3
TIMER4_TG
TIMER4_CH2
TIMER4_UP
●
TIMER4_CH1
TIMER4_CH0
TIMER5
●
●
TIMER5_UP
●
●
TIMER6
●
●
●
TIMER6_UP
●
TIMER7
TIMER7_CH2
TIMER7_CH3
TIMER7_CH0
●
TIMER7_CH1