GigaDevice Semiconductor GD32F1 0 Series User Manual (English)

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GigaDevice Semiconductor Inc.

GD32F1x0

ARM

Cortex

-M3 32-bit MCU

User Manual

Revision 3.6

(Jul. 2022)

Table of Contents2
List of Figures17
List of Tables24
System and Memory Architecture27
ARM Cortex-M3 Processor27
System Architecture28
Figure 1-1. the Structure of the Cortex28
Figure 1-2. Series System Architecture of Gd32F130Xx and Gd32F150Xx Devices29
Memory Map30
Figure 1-3. Series System Architecture of Gd32F170Xx and Gd32F190Xx Devices30
Table 1-1. Memory Map of Gd32F130Xx and Gd32F150Xx Devices31
Table 1-2. Memory Map of Gd32F170Xx and Gd32F190Xx Devices33
Bit-Banding35
On-Chip SRAM Memory35
On-Chip Flash Memory36
Boot Configuration36
Table 1-3. Flash Module Organization36
Table 1-4. Boot Modes36
System Configuration Registers (SYSCFG)38
System Configuration Register 0 (SYSCFG_CFG0)38
System Configuration Register 1 (SYSCFG_CFG1)39
EXTI Sources Selection Register 0 (SYSCFG_EXTISS0)39
EXTI Sources Selection Register 1 (SYSCFG_EXTISS1)41
EXTI Sources Selection Register 2 (SYSCFG_EXTISS2)42
EXTI Sources Selection Register 3 (SYSCFG_EXTISS3)43
System Configuration Register 2 (SYSCFG_CFG2)44
Device Electronic Signature45
Memory Density Information46
Unique Device ID (96 Bits)46
Flash Memory Controller (FMC)48
Overview48
Characteristics48
Function Overview48
Flash Memory Architecture48
Table 2-1. Base Address and Size for Flash Memory48
Read Operations49
Unlock the FMC_CTL Register49
Page Erase49
Mass Erase50
Figure 2-1. Process of Page Erase Operation50
Figure 2-2. Process of the Mass Erase Operation51
Main Flash Programming52
Option Bytes Erase53
Figure 2-3. Process of the Word Programming Operation53
Option Bytes Programming54
Option Bytes Description54
Table 2-2. Option Bytes54
Page Erase/Program Protection55
Security Protection56
Table 2-3. OB_WP Bit for Pages Protected56
Register Definition57
Wait State Register (FMC_WS)57
Unlock Key Register (FMC_KEY)57
Option Bytes Unlock Key Register (FMC_OBKEY)58
Status Register (FMC_STAT)58
Control Register (FMC_CTL)59
Address Register (FMC_ADDR)60
Option Bytes Status Register (FMC_OBSTAT)61
Write Protection Register (FMC_WP)61
Wait State Enable Register (FMC_WSEN)62
Product ID Register (FMC_PID)63
Power Management Unit (PMU)64
Overview64
Characteristics64
Function Overview64
Figure 3-1. Power Supply Overview of Gd32F130Xx and Gd32F150Xx Devices65
Backup Domain66
Figure 3-2. Power Supply Overview of Gd32F170Xx and Gd32F190Xx Devices66
Dda67
VDD Domain67
Figure 3-3. Waveform of the POR/PDR68
1.2V Power Domain for Gd32F130Xx and Gd32F150Xx Devices69
1.8V Power Domain for Gd32F170Xx and Gd32F190Xx Devices69
Figure 3-4. Waveform of LVD Threshold69
Power Saving Modes70
Table 3-1. Power Saving Mode Summary71
Register Definition72
Control Register (PMU_CTL)72
Power Control/Status Register (PMU_CS)75
Reset and Clock Unit (RCU)77
Reset Control Unit (RCTL)77
Overview77
Function Overview77
Clock Control Unit (CCTL)78
Overview78
Figure 4-1. the System Reset Circuit78
Figure 4-2. Clock Tree of Gd32F130Xx and Gd32F150Xx Devices79
Figure 4-3. Clock Tree of Gd32F170Xx and Gd32F190Xx Devices80
Characteristics81
Function Overview81
Figure 4-4. HXTAL Clock Source81
Table 4-1. Clock Source Select84
Table 4-2. Clock Source Select84
Table 4-3. Core Domain Voltage Selected in Deep-Sleep Mode85
Table 4-4. Core Domain Voltage Selected in Deep-Sleep Mode85
Register Definition86
Control Register 0 (RCU_CTL0)86
Configuration Register 0 (RCU_CFG0)87
Interrupt Register (RCU_INT)94
APB2 Reset Register (RCU_APB2RST)100
APB1 Reset Register (RCU_APB1RST)101
AHB Enable Register (RCU_AHBEN)106
APB2 Enable Register (RCU_APB2EN)107
APB1 Enable Register (RCU_APB1EN)109
Backup Domain Control Register (RCU_BDCTL)113
Reset Source /Clock Register (RCU_RSTSCK)116
AHB Reset Register (RCU_AHBRST)118
Configuration Register 1 (RCU_CFG1)119
Configuration Register 2 (RCU_CFG2)120
Control Register 1 (RCU_CTL1)122
Configuration Register 3 (RCU_CFG3) of Gd32F170Xx and Gd32F190Xx Devices123
APB1 Additional Enable Register (RCU_ADDAPB1EN)124
APB1 Additional Reset Register (RCU_ADDAPB1RST)124
Voltage Key Register (RCU_VKEY)125
Deep-Sleep Mode Voltage Register (RCU_DSV)125
Power down Voltage Select Register (RCU_PDVSEL) of Gd32F130Xx and Gd32F150Xx Devices126
Interrupt/Event Controller (EXTI)128
Overview128
Characteristics128
Interrupts Function Overview128
Table 5-1. NVIC Exception Types in Cotrex-M3129
Table 5-2. Interrupt Vector Table of Gd32F130Xx and Gd32F150Xx Devices129
Table 5-3. Interrupt Vector Table of Gd32F170Xx and Gd32F190Xx Devices130
External Interrupt and Event (EXTI) Block Diagram132
Figure 5-1. Block Diagram of EXTI132
External Interrupt and Event Function Overview133
Table 5-4. EXTI Source of Gd32F130Xx and Gd32F150Xx Devices133
Table 5-5. EXTI Source of Gd32F170Xx and Gd32F190Xx Devices134
Register Definition136
Interrupt Enable Register (EXTI_INTEN)136
Event Enable Register (EXTI_EVEN)136
Rising Edge Trigger Enable Register (EXTI_RTEN)137
Falling Edge Trigger Enable Register (EXTI_FTEN)137
Software Interrupt Event Register (EXTI_SWIEV)138
Pending Register (EXTI_PD)139
General-Purpose I/Os (GPIO)140
Overview140
Characiteristics140
Function Overview140
GPIO Pin Configuration141
Figure 6-1. Basic Structure of a General-Pupose I/O141
Table 6-1. GPIO Configuration Table141
Alternate Functions (AF)142
Additional Functions142
Input Configuration142
Figure 6-2. Basic Structure of Input Configuration142
Output Configuration143
Figure 6-3. Basic Structure of Output Configuration143
Analog Configuration144
Alternate Function (AF) Configuration144
Figure 6-4. Basic Structure of Analog Configuration144
Figure 6-5. Basic Structure of Alternate Function Configuration144
GPIO Locking Function145
GPIO Single Cycle Toggle Function145
Register Definition146
Port Control Register (Gpiox_Ctl, X=A146
Port Output Mode Register (Gpiox_Omode, X=A147
Port Output Speed Register (Gpiox_Ospd, X=A149
Port Pull-Up/Down Register (Gpiox_Pud, X=A151
Port Input Status Register (Gpiox_Istat, X=A152
Port Output Control Register (Gpiox_Octl, X=A153
Port Bit Operate Register (Gpiox_Bop, X=A153
Port Configuration Lock Register (Gpiox_Lock, X=A, B)154
Alternate Function Selected Register0 (Gpiox_Afsel0, X=A, B, C)155
Alternate Function Selected Register1 (Gpiox_Afsel1, X=A,B,C)156
Bit Clear Register (Gpiox_Bc, X=A157
Port Bit Toggle Register (Gpiox_Tg, X=A158
Cyclic Redundancy Checks Management Unit (CRC)159
Overview159
Characteristics159
Function Overview160
Figure 7-1. Block Diagram of CRC Management Unit160
Register Definition162
Data Register (CRC_DATA)162
Free Data Register (CRC_FDATA)162
Control Register (CRC_CTL)163
Initialization Data Register (CRC_IDATA)163
Direct Memory Access Controller (DMA)165
Overview165
Characteristics165
Block Diagram166
Function Overview166
DMA Operation166
Figure 8-1. Block Diagram of DMA166
Table 8-1. DMA Transfer Operation167
Peripheral Handshake168
Arbitration168
Figure 8-2. Handshake Mechanism168
Address Generation169
Circular Mode169
Memory to Memory Mode169
Channel Configuration169
Interrupt170
Figure 8-3. DMA Interrupt Logic170
Table 8-2. Interrupt Events170
DMA Request Mapping171
Table 8-3. DMA Requests for each Channel171
Figure 8-4. DMA Request Mapping172
Register Definition174
Interrupt Flag Register (DMA_INTF)174
Interrupt Flag Clear Register (DMA_INTC)174
Channel X Control Register (Dma_Chxctl)175
Channel X Counter Register (Dma_Chxcnt)177
Channel X Peripheral Base Address Register (Dma_Chxpaddr)178
Channel X Memory Base Address Register (Dma_Chxmaddr)178
Debug (DBG)180
Overview180
Serial Wire Debug Port Overview180
Pin Assignment180
JEDEC-106 ID Code180
Debug Hold Function Overview181
Debug Support for Power Saving Mode181
Debug Support for TIMER, I2C, RTC, WWDGT and FWDGT181
DBG Registers182
ID Code Register (DBG_ID)182
Control Register 0(DBG_CTL0)182
Control Register 1 (DBG_CTL1)186
Analog to Digital Converter (ADC)188
Overview188
Characteristics188
Pins and Internal Signals189
Figure 10-1. ADC Module Block Diagram of Gd32F130Xx and Gd32F150Xx Devices189
Figure 10-2. ADC Module Block Diagram of Gd32F170Xx and Gd32F190Xx Devices189
Table 10-1. ADC Internal Input Signals190
Table 10-2. ADC Input Pins Definition of Gd32F130Xx and Gd32F150Xx Devices190
Table 10-3. ADC Input Pins Definition of Gd32F170Xx and Gd32F190Xx Devices190
Function Overview191
Foreground Calibration Function192
Dual Clock Domain Architecture193
ADCON Enable193
Routine Sequence193
Operation Modes193
Figure 10-3. Single Operation Mode193
Figure 10-4. Continuous Operation Mode194
Figure 10-5. Scan Operation Mode, Continuous Disable195
Figure 10-6. Scan Operation Mode, Continuous Enable195
Conversion Result Threshold Monitor Function196
Data Storage Mode196
Figure 10-7. Discontinuous Operation Mode196
Sample Time Configuration197
Figure 10-8. Data Storage Mode of 12-Bit Resolution197
Figure 10-9. Data Storage Mode of 10-Bit Resolution197
Figure 10-10. Data Storage Mode of 8-Bit Resolution197
Figure 10-11. Data Storage Mode of 6-Bit Resolution197
External Trigger Configuration198
DMA Request198
ADC Internal Channels198
Table 10-4. External Trigger Source for ADC Routine Sequence198
Battery Voltage Monitoring199
ADC Interrupts199
Programmable Resolution (DRES)199
Table 10-5. T CONV Timings Depending on Resolution199
On-Chip Hardware Oversampling200
Figure 10-12. 20-Bit to 16-Bit Result Truncation200
Figure 10-13. Numerical Example with 5-Bits Shift and Rounding200
Table 10-6. Maximum Output Results Vs N and M (Grayed Values Indicates Truncation)201
Register Definition203
Status Register (ADC_STAT)203
Control Register 0 (ADC_CTL0)203
Control Register 1 (ADC_CTL1)206
Sampling Time Register 0 (ADC_SAMPT0)208
Sampling Time Register 1 (ADC_SAMPT1)210
Watchdog High Threshold Register (ADC_WDHT)211
Watchdog Low Threshold Register (ADC_WDLT)211
Routine Sequence Register 0 (ADC_RSQ0)212
Routine Sequence Register 1 (ADC_RSQ1)212
Routine Sequence Register 2 (ADC_RSQ2)213
Routine Data Register (ADC_RDATA)213
Oversampling Control Register (ADC_OVSAMPCTL)214
Digital-To-Analog Converter (DAC)216
Overview216
Characteristic216
Figure 11-1. DAC Block Diagram216
Function Overview217
DAC Enable217
DAC Output Buffer217
Table 11-1. DAC I/O Description217
DAC Data Configuration218
DAC Trigger218
Table 11-2. External Triggers of DAC218
DAC Workflow219
DAC Output Calculate219
DMA Function219
DAC Concurrent Conversion for Gd32F190Xx Devices219
Register Definition221
Control Register (DAC_CTL)221
Software Trigger Register (DAC_SWT)224
DAC0 12-Bit Right-Aligned Data Holding Register (DAC0_R12DH)225
DAC0 12-Bit Left-Aligned Data Holding Register (DAC0_L12DH)225
DAC0 8-Bit Right-Aligned Data Holding Register (DAC0_R8DH)226
DAC1 12-Bit Right-Aligned Data Holding Register (DAC1_R12DH) of Gd32F190Xx Devices226
DAC1 12-Bit Left-Aligned Data Holding Register (DAC1_L12DH) of Gd32F190Xx Devices227
DAC1 8-Bit Right-Aligned Data Holding Register (DAC1_R8DH) of Gd32F190Xx Devices227
DAC Concurrent Mode 12-Bit Right-Aligned Data Holding Register (DACC_R12DH) of228
Gd32F190Xx Devices228
Gd32F190Xx Devices229
DAC0 Data Output Register (DAC0_DO)230
DAC1 Data Output Register (DAC1_DO) of Gd32F190Xx Devices230
Status Register (DAC_STAT)230
Comparator (CMP)233
Overview233
Characteristics233
Function Overview233
Figure 12-1. CMP Block Diagram of Gd32F150Xx Devices234
Figure 12-2. CMP Block Diagram of Gd32F190Xx Devices234
CMP Clock and Reset235
CMP I/O Configure235
CMP Operating Mode235
CMP Hysteresis235
CMP Register Write Protection236
Figure 12-3. CMP Hysteresis236
Register Definition237
Control/Status Register (CMP_CS)237
Watchdog Timer (WDGT)244
Free Watchdog Timer (FWDGT)244
Overview244
Characteristics244
Function Overview244
Figure 13-1. Free Watchdog Timer Block Diagram245
Table 13-1. Min / Max FWDGT Timeout Period at 40 Khz (IRC40K)246
Register Definition247
Window Watchdog Timer (WWDGT)251
Overview251
Characteristics251
Function Overview251
Figure 13-2. Window Watchdog Timer Block Diagram252
Figure 13-3. Window Watchdog Timer Timing Diagram253
Table 13-2. Min-Max Timeout Value at 36 Mhz (Fpclk1)253
Register Definition254
Real-Time Clock(RTC)256
Overview256
Characteristics256
Function Overview257
Block Diagram257
Clock Source and Prescalers257
Figure 14-1. Block Diagram of RTC257
Shadow Registers Introduction258
Configurable and Field Maskable Alarm258
RTC Initialization and Configuration259
Calendar Reading260
Resetting the RTC261
RTC Shift Function261
RTC Reference Clock Detection262
RTC Smooth Digital Calibration263
Time-Stamp Function265
Tamper Detection265
Calibration Clock Output266
Alarm Output266
RTC Power Saving Mode Management267
RTC Interrupts267
Table 14-1. RTC Power Saving Mode Management267
Table 14-2. RTC Interrupts Control267
Register Definition268
Time Register (RTC_TIME)268
Date Register (RTC_DATE)268
Control Register (RTC_CTL)269
Status Register (RTC_STAT)271
Prescaler Register (RTC_PSC)273
Alarm 0 Time and Date Register (RTC_ALRM0TD)274
Write Protection Key Register (RTC_WPK)275
Sub Second Register (RTC_SS)275
Shift Function Control Register (RTC_SHIFTCTL)276
Time of Time Stamp Register (RTC_TTS)276
Date of Time Stamp Register (RTC_DTS)277
Sub Second of Time Stamp Register (RTC_SSTS)278
High Resolution Frequency Compensation Register (RTC_HRFC)278
Tamper Register (RTC_TAMP)279
Alarm 0 Sub Second Register (RTC_ALRM0SS)281
Backup Registers (Rtc_Bkpx) (X=0282
Timer (Timerx)284
Table 15-1. Timers (Timerx) Are Devided into Six Sorts284
Advanced Timer (Timerx,X=0)285
Overview285
Characteristics285
Block Diagram286
Function Overview286
Figure 15-1. Advanced Timer Block Diagram286
Figure 15-2. Timing Chart of Internal Clock Divided by 1287
Figure 15-3. Timing Chart of PSC Value Change from 0 to 2288
Figure 15-4. Timing Chart of up Counting Mode, PSC=0/2289
Figure 15-5. Timing Chart of up Counting Mode, Change Timerx_Car on the Go289
Figure 15-6. Timing Chart of down Counting Mode, PSC=0/2290
Figure 15-7. Timing Chart of down Counting Mode, Change Timerx_Car on the Go291
Figure 15-8. Center-Aligned Counter Timechart291
Figure 15-9. Repetition Counter Timing Chart of Center-Aligned Counting Mode293
Figure 15-10. Repetition Counter Timing Chart of up Counting Mode293
Figure 15-11. Repetition Counter Timing Chart of down Counting Mode294
Figure 15-12. Channel Input Capture Principle295
Figure 15-13. Channel Output Compare Principle (with Complementary Output296
Figure 15-14. Channel Output Compare Principle (CH3_O)296
Figure 15-15. Output-Compare under Three Modes297
Figure 15-16. EAPWM Timechart299
Figure 15-17. CAPWM Timechart299
Table 15-2. Complementary Outputs Controlled by Parameters300
Figure 15-18. Channel Output Complementary PWM with Dead-Time Insertion302
Figure 15-19. Output Behavior in Response to a Break(the Break High Active)303
Table 15-3. Counting Direction Versus Encoder Signals303
Figure 15-20. Example of Counter Operation in Encoder Interface Mode304
Figure 15-21. Example of Encoder Interface Mode with CI0FE0 Polarity Inverted304
Figure 15-22. Hall Sensor Is Used to BLDC Motor304
Figure 15-23. Hall Sensor Timing between Two Timers306
Table 15-4. Slave Mode Example Table306
Figure 15-24. Restart Mode307
Figure 15-25. Pause Mode307
Figure 15-26. Event Mode308
Figure 15-27. Single Pulse Mode Timerx_Chxcv = 0X04 Timerx_Car=0X60309
Figure 15-28. TIMER0 Master/Slave Mode Timer Example309
Table 15-5. Input Trigger of Timer0310
Figure 15-29. Triggering TIMER0 with Enable of TIMER2311
Figure 15-30. Triggering TIMER0 and TIMER2 with Timer2'S CI0 Input312
Timerx Registers(X=0)313
General Level0 Timer (Timerx, X=1, 2)341
Overview341
Characteristics341
Block Diagram341
Figure 15-31. General Level 0 Timer Block Diagram341
Function Overview342
Figure 15-32. Timing Chart of Internal Clock Divided by 1343
Figure 15-33. Timing Chart of PSC Value Change from 0 to 2344
Figure 15-34. Timing Chart of up Counting Mode, PSC=0/2344
Figure 15-35. Timing Chart of up Counting Mode, Change Timerx_Car on the Go345
Figure 15-36. Timing Chart of down Counting Mode, PSC=0/2346
Figure 15-37. Timing Chart of down Counting Mode, Change Timerx_Car on the Go347
Figure 15-38. Center-Aligned Counter Timechart347
Figure 15-39. Channel Input Capture Principle349
Figure 15-40. Channel Output Compare Principle (X=0,1,2,3)350
Figure 15-41. Output-Compare under Three Modes351
Figure 15-42. Timing Chart of EAPWM351
Figure 15-43. Timing Chart of CAPWM352
Table 15-6. Timerx(X=1,2) Interconnection353
Timerx Registers(X=1, 2)355
General Level2 Timer (Timerx, X=13)381
Overview381
Characteristics381
Block Diagram381
Figure 15-44. General Level2 Timer Block Diagram381
Function Overview382
Figure 15-45. Timing Chart of Internal Clock Divided by 1383
Figure 15-46. Timing Chart of PSC Value Change from 0 to 2383
Figure 15-47. Timing Chart of up Counting Mode, PSC=0/2384
Figure 15-48. Timing Chart of up Counting Mode, Change Timerx_Car on the Go385
Figure 15-49. Channel Input Capture Principle386
Figure 15-51. Output-Compare under Three Modes388
Figure 15-52. PWM Mode Timechart388
Timerx Registers(X=13)390
General Level3 Timer (Timerx, X=14)401
Overview401
Characteristics401
Block Diagram401
Figure 15-53. General Level3 Timer Block Diagram401
Figure 15-54. Timing Chart of Internal Clock Divided by 1403
Figure 15-55. Timing Chart of PSC Value Change from 0 to 2404
Figure 15-56. Timing Chart of up Counting Mode, PSC=0/2405
Figure 15-57. Timing Chart of up Counting Mode, Change Timerx_Car on the Go405
Figure 15-58. Repetition Counter Timing Chart of up Counting Mode406
Figure 15-59. Channel Input Capture Principle407
Figure 15-50. Channel Output Compare Principle408
Figure 15-60. Channel Output Compare Principle (with Complementary Output, X=0)408
Figure 15-61. Channel Output Compare Principle (CH1_O)408
Figure 15-62. Output-Compare under Three Modes409
Figure 15-63. PWM Mode Timechart410
Table 15-7. Complementary Outputs Controlled by Parameters412
Figure 15-64. Complementary Output with Dead-Time Insertion413
Figure 15-65. Output Behavior in Response to a Break(the Break High Active)414
Table 15-8. Slave Mode Example Table414
Figure 15-66. Restart Mode415
Figure 15-67. Pause Mode415
Figure 15-68. Event Mode416
Figure 15-69. Single Pulse Mode Timerx_Chxcv = 4 Timerx_Car=99416
Table 15-9. Timerx(X=14) Interconnection417
Figure 15-70. General Level4 Timer Block Diagram438
Figure 15-71. Timing Chart of Internal Clock Divided by 1440
Figure 15-72. Timing Chart of PSC Value Change from 0 to 2440
Figure 15-73. Timing Chart of up Counting Mode, PSC=0/2441
Figure 15-74. Timing Chart of up Counting Mode, Change Timerx_Car on the Go442
Figure 15-75. Repetition Counter Timing Chart of up Counting Mode443
Figure 15-76. Channel Input Capture Principle444
Figure 15-77. Output-Compare under Three Modes445
Figure 15-78. PWM Mode Timechart446
Table 15-10. Complementary Outputs Controlled by Parameters448
Figure 15-79. Channel Output Complementary PWM with Dead-Time Insertion449
Figure 15-80. Output Behavior in Response to a Break(the Break High Active)450
Figure 15-81. Single Pulse Mode Timerx_Chxcv = 0X04 Timerx_Car=0X60451
Figure 15-82. Basic Timer Block Diagram468
Figure 15-83. Timing Chart of Internal Clock Divided by 1469
Figure 15-84. Timing Chart of PSC Value Change from 0 to 2470
Figure 15-85. Timing Chart of up Counting Mode, PSC=0/2471
Figure 15-86. Timing Chart of up Counting Mode, Change Timerx_Car on the Go471
Figure 16-1. IFRP Output Timechart 1478
Figure 16-2. IFRP Output Timechart 2479
Figure 16-3. IFRP Output Timechart 3479
Figure 17-1. USART Module Block Diagram482
Table 17-1. USART Important Pins Description482
Figure 17-2. USART Character Frame (8 Bits Data and 1 Stop Bit)483
Table 17-2. Stop Bits Configuration483
Figure 17-3. USART Transmit Procedure485
Figure 17-4. Oversampling Method of a Receive Frame Bit (OSB=0)486
Figure 17-5. Configuration Step When Using DMA for USART Transmission487
Figure 17-6. Configuration Step When Using DMA for USART Reception488
Figure 17-7. Hardware Flow Control between Two Usarts488
Figure 17-8. Hardware Flow Control489
Figure 17-9. Break Frame Occurs During Idle State490
Figure 17-10. Break Frame Occurs During a Frame491
Figure 17-11. Example of USART in Synchronous Mode491
Figure 17-12. 8-Bit Format USART Synchronous Waveform (CLEN=1)492
Figure 17-13. Irda SIR ENDEC Module492
Figure 17-14. Irda Data Modulation493
Figure 17-15. ISO7816-3 Frame Format494
Table 17-3. USART Interrupt Requests496
Figure 17-16. USART Interrupt Mapping Diagram497
Figure 18-1. I2C Module Block Diagram516
Table 18-1. Definition of I2C-Bus Terminology (Refer to the I2C Specification of Philips Semiconductors)517
Figure 18-2. Data Validation518
Figure 18-3. START and STOP Signal518
Figure 18-4. Clock Synchronization519
Figure 18-5. SDA Line Arbitration519
Figure 18-6. I2C Communication Flow with 7-Bit Address520
Figure 18-7. I2C Communication Flow with 10-Bit Address (Master Transmit)520
Figure 18-8. I2C Communication Flow with 10-Bit Address (Master Receive)520
Figure 18-9. Programming Model for Slave Transmitting (10-Bit Address Mode)520
Figure 18-10. Programming Model for Slave Receiving (10-Bit Address Mode)522
Figure 18-11. Programming Model for Master Transmitting (10-Bit Address Mode)523
Figure 18-12. Programming Model for Master Receiving Using Solution a (10-Bit Address Mode)527
Figure 18-13. Programming Model for Master Receiving Mode Using Solution B (10-Bit Address Mode)528
Table 18-2. Event Status Flags532
Table 18-3. Error Flags533
Figure 19-1. Block Diagram of SPI for Gd32F130Xx and Gd32F150Xx Devices546
Figure 19-2. Block Diagram of SPI for Gd32F170Xx and Gd32F190Xx Devices546
Table 19-1. SPI Signal Description546
Table 19-2. Quad-SPI Signal Description547
Figure 19-3. SPI Timing Diagram in Normal Mode548
Figure 19-4. SPI Timing Diagram in Quad-SPI Mode (CKPL=1, CKPH=1, LF=0) for Gd32F170Xx and Gd32F190Xx Devices548
Table 19-3. NSS Function in Slave Mode549
Table 19-4. NSS Function in Master Mode549
Table 19-5. SPI Operation Modes550
Figure 19-5. a Typical Full-Duplex Connection551
Figure 19-6. a Typical Simplex Connection (Master: Receive, Slave: Transmit)551
Figure 19-7. a Typical Simplex Connection (Master: Transmit Only, Slave: Receive)551
Figure 19-8. a Typical Bidirectional Connection552
Figure 19-9. Timing Diagram of Write Operation in Quad-SPI Mode554
Figure 19-10. Timing Diagram of Read Operation in Quad-SPI Mode555
Table 19-6. SPI Interrupt Requests557
Figure 19-11. Block Diagram of I2S558
Figure 19-12. I2S Phillips Standard Timing Diagram (DTLEN=00, CHLEN=0, CKPL=0)559
Figure 19-13. I2S Phillips Standard Timing Diagram (DTLEN=00, CHLEN=0, CKPL=1)559
Figure 19-14. I2S Phillips Standard Timing Diagram (DTLEN=10, CHLEN=1, CKPL=0)559
Figure 19-15. I2S Phillips Standard Timing Diagram (DTLEN=10, CHLEN=1, CKPL=1)560
Figure 19-16. I2S Phillips Standard Timing Diagram (DTLEN=01, CHLEN=1, CKPL=0)560
Figure 19-17. I2S Phillips Standard Timing Diagram (DTLEN=01, CHLEN=1, CKPL=1)560
Figure 19-18. I2S Phillips Standard Timing Diagram (DTLEN=00, CHLEN=1, CKPL=0)560
Figure 19-19. I2S Phillips Standard Timing Diagram (DTLEN=00, CHLEN=1, CKPL=1)561
Figure 19-20. MSB Justified Standard Timing Diagram (DTLEN=00, CHLEN=0, CKPL=0)561
Figure 19-21. MSB Justified Standard Timing Diagram (DTLEN=00, CHLEN=0, CKPL=1)561
Figure 19-22. MSB Justified Standard Timing Diagram (DTLEN=10, CHLEN=1, CKPL=0)561
Figure 19-23. MSB Justified Standard Timing Diagram (DTLEN=10, CHLEN=1, CKPL=1)561
Figure 19-24. MSB Justified Standard Timing Diagram (DTLEN=01, CHLEN=1, CKPL=0)562
Figure 19-25. MSB Justified Standard Timing Diagram (DTLEN=01, CHLEN=1, CKPL=1)562
Figure 19-26. MSB Justified Standard Timing Diagram (DTLEN=00, CHLEN=1, CKPL=0)562
Figure 19-27. MSB Justified Standard Timing Diagram (DTLEN=00, CHLEN=1, CKPL=1)562
Figure 19-28. LSB Justified Standard Timing Diagram (DTLEN=01, CHLEN=1, CKPL=0)562
Figure 19-29. LSB Justified Standard Timing Diagram (DTLEN=01, CHLEN=1, CKPL=1)563
Figure 19-30. LSB Justified Standard Timing Diagram (DTLEN=00, CHLEN=1, CKPL=0)563
Figure 19-31. LSB Justified Standard Timing Diagram (DTLEN=00, CHLEN=1, CKPL=1)563
Figure 19-32. PCM Standard Short Frame Synchronization Mode Timing Diagram (DTLEN=00, CHLEN=0, CKPL=0)563
Figure 19-33. PCM Standard Short Frame Synchronization Mode Timing Diagram (DTLEN=00, CHLEN=0, CKPL=1)564
Figure 19-34. PCM Standard Short Frame Synchronization Mode Timing Diagram (DTLEN=10, CHLEN=1, CKPL=0)564
Figure 19-35. PCM Standard Short Frame Synchronization Mode Timing Diagram (DTLEN=10, CHLEN=1, CKPL=1)564
Figure 19-36. PCM Standard Short Frame Synchronization Mode Timing Diagram (DTLEN=01, CHLEN=1, CKPL=0)564
Figure19-37. PCM Standard Short Frame Synchronization Mode Timing Diagram (DTLEN=01, CHLEN=1, CKPL=1)564
Figure 19-38. PCM Standard Short Frame Synchronization Mode Timing Diagram (DTLEN=00, CHLEN=1, CKPL=0)565
Figure 19-39. PCM Standard Short Frame Synchronization Mode Timing Diagram (DTLEN=00, CHLEN=1, CKPL=1)565
Figure 19-40. PCM Standard Long Frame Synchronization Mode Timing Diagram (DTLEN=00, CHLEN=0, CKPL=0)565
Figure19-41. PCM Standard Long Frame Synchronization Mode Timing Diagram (DTLEN=00, CHLEN=0, CKPL=1)565
Figure 19-42. PCM Standard Long Frame Synchronization Mode Timing Diagram (DTLEN=10, CHLEN=1, CKPL=0)565
Figure 19-43. PCM Standard Long Frame Synchronization Mode Timing Diagram565
Figure 19-44. PCM Standard Long Frame Synchronization Mode Timing Diagram (DTLEN=01, CHLEN=1, CKPL=0)566
Figure 19-45. PCM Standard Long Frame Synchronization Mode Timing Diagram (DTLEN=01, CHLEN=1, CKPL=1)566
Figure 19-46. PCM Standard Long Frame Synchronization Mode Timing Diagram (DTLEN=00, CHLEN=1, CKPL=0)566
Figure 19-47. PCM Standard Long Frame Synchronization Mode Timing Diagram (DTLEN=00, CHLEN=1, CKPL=1)566
Figure 19-48. Block Diagram of I2S Clock Generator567
Table 19-7. I2S Bitrate Calculation Formulas567
Table 19-8. Audio Sampling Frequency Calculation Formulas567
Figure 19-49. I2S Initialization Sequence568
Table 19-9. Direction of I2S Interface Signals for each Operation Mode568
Figure 19-50. I2S Master Reception Disabling Sequence571
Table 19-10. I2S Interrupt573
Figure 20-1. HDMI-CEC Controller Block Diagram585
Figure 20-2. Message Structure585
Table 20-1. Frame Structure585
Figure 20-3. Start Bit Timing586
Figure 20-4. Data Bit Timing586
Table 20-2. Data Bit Timing Parameter Table586
Figure 20-5. the Process of CEC Line Arbitration587
Figure 20-6. the Free Time of Signal587
Table 20-3. the Relationship Betwwen Signal Free Time and Precondition588
Figure 20-7. Erro Bit Period589
Figure 20-8. the Timing of Bit Period Long Error590
Table 20-4. Error Handling Timing Parameter Table590
Figure 20-9. Transmission Error Detection591
Table 20-5. TERR Timing Parameter Table591
Table 20-6. HDMI-CEC Interrupt592
Figure 21-1. Block Diagram of TSI Module601
Figure 21-2. Block Diagram of Sample Pin and Channel Pin602
Table 21-1. Pin and Analog Switch State in a Charge-Transfer Sequence603
Figure 21-3. Voltage of a Sample Pin During Charge-Transfer Sequence604
Figure 21-4. FSM Flow of a Charge-Transfer Sequence605
Table 21-2. Duration Time of Extend Charge State in each Cycle606
Table 21-3. TSI Errors and Flags608
Table 21-4. TSI Pins608
Figure 22-1. USBD Block Diagram617
Table 22-1. USBD Signal Description618
Figure 22-2. an Example with Buffer Descriptor Table Usage (USBD_BADDR = 0)620
Table 22-2. Double-Buffering Buffer Flag Definition621
Table 22-3. Double Buffer Usage621
Table 22-4. Reception Status Encoding633
Table 22-5. Endpoint Type Encoding634
Table 22-6. Endpoint Kind Meaning634
Table 22-7. Transmission Status Encoding634
Figure 23-1. SLCD Block Diagram638
Figure 23-2. 1/3 Bias, 1/4 Duty639
Table 23-1. the Odd Frame Voltage639
Table 23-2. the Even Frame Voltage640
Table 23-3. the All Common Signal Driver640
Figure 23-3. 1/4 Bias, 1/6 Duty641
Figure 23-4. SLCD Dead Time (1/3 Bias, 1/4 Duty)641
Figure 24-1. OPA0 Signal Route651
Figure 24-2. OPA1 Signal Route651
Figure 24-3. OPA2 Signal Route651
Table 24-1. Operating Mode and Calibration652
Figure 26-1. CAN Module Block Diagram664
Figure 26-2. Transmission Register666
Figure 26-3. State of Transmission Mailbox667
Figure 26-4. Reception Register668
Figure 26-5. 32-Bit Filter669
Figure 26-6. 16-Bit Filter670
Figure 26-7. 32-Bit Mask Mode Filter670
Figure 26-8. 16-Bit Mask Mode Filter670
Figure 26-9. 32-Bit List Mode Filter670
Figure 26-10. 16-Bit List Mode Filter670
Table 26-1. 32-Bit Filter Number671
Table 26-2. Filtering Index671
Figure 26-11. the Bit Time674
Figure 26-12. CAN PHY Connection677
Table 27-1. List of Abbreviations Used in Register698

Core	ARM Cortex-M3
Operating Frequency	Up to 108 MHz
GPIO Pins	Up to 80
Operating Temperature	-40°C to +85°C
Debug Interface	SWD, JTAG
ADC	12-bit
DAC	12-bit
Communication Interfaces	USART, SPI, I2C, USB
Operating Voltage	2.6 V to 3.6 V
Package	LQFP, QFN

GigaDevice Semiconductor GD32F1 0 Series User Manual

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GigaDevice Semiconductor GD32F1 0 Series Specifications

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