GigaDevice Semiconductor GD32F3 0 Series

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GigaDevice Semiconductor Inc.

GD32F3x0

Arm

Cortex

-M4 32-bit MCU

(Applicable to GD32F310, GD32GD32F330,

GD32GD32F350 series)

User Manual

Revision 2.8

(Jun. 2023)

Main Page

Table of Contents3
List of Figures16
List of Table22
System and Memory Architecture24
Arm ® Cortex ® -M4 Processor24
Figure 1-1. the Structure of the Cortex -M4 Processor24
System Architecture25
Memory Map26
Figure 1-2. Series System Architecture of Gd32F3X0 Series26
Table 1-1. Memory Map of Gd32F3X0 Series27
Bit-Banding29
On-Chip SRAM Memory29
On-Chip Flash Memory30
Boot Configuration30
Table 1-2. Flash Module Organization30
I / O Compensation Cell31
Table 1-3. Boot Modes31
System Configuration Registers (SYSCFG)32
System Configuration Register 0 (SYSCFG_CFG0)32
EXTI Sources Selection Register 0 (SYSCFG_EXTISS0)33
EXTI Sources Selection Register 1 (SYSCFG_EXTISS1)34
EXTI Sources Selection Register 2 (SYSCFG_EXTISS2)35
EXTI Sources Selection Register 3 (SYSCFG_EXTISS3)37
System Configuration Register 2 (SYSCFG_CFG2)38
I / O Compensation Control Register (SYSCFG_CPSCTL)39
Device Electronic Signature40
Memory Density Information40
Unique Device ID (96 Bits)40
Flash Memory Controller (FMC)42
Overview42
Characteristics42
Function Overview42
Flash Memory Architecture42
Table 2-1. Base Address and Size for Flash Memory42
Read Operations43
Unlock the FMC_CTL Register43
Page Erase43
Mass Erase44
Figure 2-1. Process of Page Erase Operation44
Figure 2-2. Process of the Mass Erase Operation45
Main Flash Programming46
Option Byte Erase47
Figure 2-3. Process of the Word Programming Operation47
Option Byte Programming48
Option Byte Description48
Table 2-2. Option Byte48
Page Erase/Program Protection49
Security Protection50
Table 2-3. OB_WP Bit for Pages Protected50
Register Definition51
Wait State Register (FMC_WS)51
Unlock Key Register (FMC_KEY)51
Option Byte Unlock Key Register (FMC_OBKEY)52
Status Register (FMC_STAT)52
Control Register (FMC_CTL)53
Address Register (FMC_ADDR)54
Option Byte Status Register (FMC_OBSTAT)55
Write Protection Register (FMC_WP)55
Wait State Enable Register (FMC_WSEN)56
Product ID Register (FMC_PID)56
Power Management Unit (PMU)58
Overview58
Characteristics58
Function Overview58
Figure 3-1. Power Supply Overview58
Backup Domain59
VDD59
DD DDA Power Domain60
Figure 3-2. Waveform of the por / PDR60
Figure 3-3. Waveform of the LVD Threshold61
Power Domain62
Power Saving Modes62
Table 3-1. Power Saving Mode Summary64
Register Definition66
Control Register (PMU_CTL)66
Control and Status Register (PMU_CS)68
Reset and Clock Unit (RCU)71
Reset Control Unit (RCTL)71
Overview71
Function Overview71
Clock Control Unit (CCTL)72
Overview72
Figure 4-1. the System Reset Circuit72
Figure 4-2. Clock Tree73
Characteristics74
Function Overview74
Figure 4-3. HXTAL Clock Source74
Figure 4-4. HXTAL Clock Source in Bypass Mode75
Table 4-1. Clock Source Select77
Table 4-2. Core Domain Voltage Selected in Deep-Sleep Mode78
Register Definition79
Control Register0 (RCU_CTL0)79
Configuration Register 0 (RCU_CFG0)80
Interrupt Register (RCU_INT)84
APB2 Reset Register (RCU_APB2RST)87
APB1 Reset Register (RCU_APB1RST)88
AHB Enable Register (RCU_AHBEN)90
APB2 Enable Register (RCU_APB2EN)92
APB1 Enable Register (RCU_APB1EN)93
Backup Domain Control Register (RCU_BDCTL)95
Reset Source /Clock Register (RCU_RSTSCK)97
AHB Reset Register (RCU_AHBRST)98
Configuration Register 1 (RCU_CFG1)100
Configuration Register 2 (RCU_CFG2)101
Control Register 1 (RCU_CTL1)102
Additional Clock Control Register (RCU_ADDCTL)102
Additional Clock Interrupt Register (RCU_ADDINT)103
APB1 Additional Enable Register (RCU_ADDAPB1EN)104
APB1 Additional Reset Register (RCU_ADDAPB1RST)105
Voltage Key Register (RCU_VKEY)105
Deep-Sleep Mode Voltage Register (RCU_DSV)106
Clock Trim Controller (CTC)107
Overview107
Characteristics107
Function Overview107
Figure 5-1. CTC Overview107
REF Sync Pulse Generator108
CTC Trim Counter108
Frequency Evaluation and Automatically Trim Process109
Figure 5-2. CTC Trim Counter109
Software Program Guide110
Register Definition111
Control Register 0 (CTC_CTL0)111
Control Register 1 (CTC_CTL1)112
Status Register (CTC_STAT)113
Interrupt Clear Register (CTC_INTC)115
Interrupt/Event Controller (EXTI)117
Overview117
Characteristics117
Interrupts Function Overview117
Table 6-1. NVIC Exception Types in Cortex ® -M4117
Table 6-2. Interrupt Vector Table118
External Interrupt and Event Block Diagram120
External Interrupt and Event Function Overview120
Figure 6-1. Block Diagram of EXTI120
Table 6-3. EXTI Source120
Register Definition123
Interrupt Enable Register (EXTI_INTEN)123
Event Enable Register (EXTI_EVEN)123
Rising Edge Trigger Enable Register (EXTI_RTEN)124
Falling Edge Trigger Enable Register (EXTI_FTEN)124
Software Interrupt Event Register (EXTI_SWIEV)125
Pending Register (EXTI_PD)125
General-Purpose and Alternate-Function I/Os (GPIO)127
Overview127
Characteristics127
Function Overview127
GPIO Pin Configuration128
Figure 7-1. Basic Structure of of a General-Pupose I/O128
Table 7-1. GPIO Configuration Table128
Alternate Functions (AF)129
Additional Functions129
Input Configuration129
Figure 7-2. Basic Structure of Input Configuration129
Output Configuration130
Analog Configuration130
Figure 7-3. Basic Structure of Output Configuration130
Alternate Function (AF) Configuration131
Figure 7-4. Basic Structure of Analog Configuration131
Figure 7-5. Basic Structure of Alternate Function Configuration131
GPIO Locking Function132
GPIO Single Cycle Toggle Function132
GPIO very High Speed Drive Capability132
Register Definition133
Port Control Register (Gpiox_Ctl, X=A133
Port Output Mode Register (Gpiox_Omode, X=A134
Port Output Speed Register 0 (Gpiox_Ospd0, X=A136
Port Pull-Up/Down Register (Gpiox_Pud, X=A138
Port Input Status Register (Gpiox_Istat, X=A139
Port Output Control Register (Gpiox_Octl, X=A140
Port Bit Operate Register (Gpiox_Bop, X=A140
Port Configuration Lock Register (Gpiox_Lock, X=A,B)141
Alternate Function Selected Register 0 (Gpiox_Afsel0, X=A,B,C)142
Alternate Function Selected Register 1 (Gpiox_Afsel1, X=A,B,C)143
Bit Clear Register (Gpiox_Bc, X=A144
Port Bit Toggle Register (Gpiox_Tg, X=A144
Port Output Speed Register 1 (Gpiox_Ospd1, X=A145
Cyclic Redundancy Checks Management Unit (CRC)146
Overview146
Characteristics146
Figure 8-1. Block Diagram of CRC Calculation Unit146
Function Overview147
Register Definition148
Data Register (CRC_DATA)148
Free Data Register (CRC_FDATA)148
Control Register (CRC_CTL)149
Initialization Data Register (CRC_IDATA)149
Polynomial Register (CRC_POLY)150
Direct Memory Access Controller (DMA)151
Overview151
Characteristics151
Block Diagram152
Function Overview152
DMA Operation152
Figure 9-1. Block Diagram of DMA152
Table 9-1. DMA Transfer Operation153
Peripheral Handshake154
Arbitration154
Figure 9-2. Handshake Mechanism154
Address Generation155
Circular Mode155
Memory to Memory Mode155
Channel Configuration155
Interrupt156
Figure 9-3. DMA Interrupt Logic156
Table 9-2. Interrupt Events156
DMA Request Mapping157
Figure 9-4. DMA Request Mapping158
Table 9-3. DMA Requests for each Channel159
Register Definition160
Interrupt Flag Register (DMA_INTF)160
Interrupt Flag Clear Register (DMA_INTC)160
Channel X Control Register (Dma_Chxctl)161
Channel X Counter Register (Dma_Chxcnt)163
Channel X Peripheral Base Address Register (Dma_Chxpaddr)164
Channel X Memory Base Address Register (Dma_Chxmaddr)164
Debug (DBG)166
Overview166
Serial Wire Debug Port Overview166
Pin Assignment166
JEDEC-106 ID Code166
Debug Hold Function Overview167
Debug Support for Power Saving Mode167
Debug Support for TIMER, I2C, RTC, WWDGT and FWDGT167
Register Definition168
ID Code Register (DBG_ID)168
Control Register 0 (DBG_CTL0)168
Control Register 1 (DBG_CTL1)170
Analog to Digital Converter (ADC)172
Overview172
Characteristics172
Pins and Internal Signals173
Figure 11-1. ADC Module Block Diagram173
Table 11-1. ADC Internal Input Signals173
Table 11-2. ADC Input Pins Definition173
Function Overview174
Foreground Calibration Function174
Dual Clock Domain Architecture175
ADCON Enable175
Routine Sequence175
Operation Modes175
Figure 11-2. Single Operation Mode175
Figure 11-3. Continuous Operation Mode176
Figure 11-4. Scan Operation Mode, Continuous Disable177
Figure 11-5. Scan Operation Mode, Continuous Enable177
Conversion Result Threshold Monitor Function178
Data Storage Mode178
Figure 11-6. Discontinuous Operation Mode178
Figure 11-8. Data Storage Mode of 10-Bit Resolution178
Sample Time Configuration179
External Trigger Configuration179
Figure 11-7. Data Storage Mode of 12-Bit Resolution179
Figure 11-9. Data Storage Mode of 8-Bit Resolution179
Figure 11-10. Data Storage Mode of 6-Bit Resolution179
DMA Request180
ADC Internal Channels180
Table 11-3. External Trigger Source for ADC180
ADC Interrupts181
Programmable Resolution (DRES)181
On-Chip Hardware Oversampling181
Table 11-4. T CONV Timings Depending on Resolution181
Figure 11-11. 20-Bit to 16-Bit Result Truncation182
Figure 11-12. Numerical Example with 5-Bits Shift and Rounding182
Table 11-5. Maximum Output Results for N and M Combimations (Grayed Values Indicates Truncation)183
Register Definition184
Status Register (ADC_STAT)184
Control Register 0 (ADC_CTL0)184
Control Register 1 (ADC_CTL1)186
Sampling Time Register 0 (ADC_SAMPT0)188
Sampling Time Register 1 (ADC_SAMPT1)188
Watchdog High Threshold Register (ADC_WDHT)189
Watchdog Low Threshold Register (ADC_WDLT)190
Routine Sequence Register0(ADC_RSQ0)190
Routine Sequence Register1(ADC_RSQ1)191
Routine Sequence Register 2 (ADC_RSQ2)191
Routine Data Register (ADC_RDATA)192
Oversampling Control Register (ADC_OVSAMPCTL)192
Digital-To-Analog Converter (DAC)195
Overview195
Characteristic195
Figure 12-1. DAC Block Diagram195
Function Overview196
DAC Enable196
DAC Output Buffer196
DAC Data Configuration196
DAC Trigger196
Table 12-1. DAC I/O Description196
Table 12-2. External Triggers of DAC196
DAC Workflow197
DAC Noise Wave197
Figure 12-2. DAC LFSR Algorithm197
DAC Output Calculate198
DMA Function198
Figure 12-3. DAC Triangle Noise Wave198
Registers Definition199
Control Register (DAC_CTL)199
Software Trigger Register (DAC_SWT)200
DAC 12-Bit Right-Aligned Data Holding Register(DAC_R12DH)201
DAC 12-Bit Left-Aligned Data Holding Register(DAC_L12DH)201
DAC 8-Bit Right-Aligned Data Holding Register (DAC_R8DH)202
DAC Data Output Register (DAC_DO)202
DAC Status Register (DAC_STAT)202
Comparator (CMP)204
Overview204
Characteristic204
Function Overview204
CMP Clock and Reset205
CMP I/O Configure205
Figure 13-1. CMP Block Diagram of Gd32F3X0 Series205
CMP Operating Mode206
CMP Hysteresis206
CMP Register Write Protection206
Figure 13-2. CMP Hysteresis206
CMP Registers207
Control/Status Register (CMP_CS)207
Watchdog Timer (WDGT)211
Free Watchdog Timer (FWDGT)211
Overview211
Characteristics211
Function Overview211
Figure 14-1. Free Watchdog Timer Block Diagram211
Table 14-1. Min/Max FWDGT Timeout Period at 40 Khz (IRC40K)213
Register Definition214
Window Watchdog Timer (WWDGT)218
Overview218
Characteristics218
Function Overview218
Figure 14-2. Window Watchdog Timer Block Diagram218
Figure 14-3. Window Watchdog Timer Timing Diagram219
Table 14-2. Min-Max Timeout Value at 54 Mhz220
Register Definition221
Real-Time Clock (RTC)223
Overview223
Characteristics223
Function Overview224
Block Diagram224
Clock Source and Prescalers224
Figure 15-1. Block Diagram of RTC224
Shadow Registers Introduction225
Configurable and Field Maskable Alarm225
RTC Initialization and Configuration226
Calendar Reading227
Resetting the RTC228
RTC Shift Function228
RTC Reference Clock Detection229
RTC Smooth Digital Calibration230
Time-Stamp Function232
Tamper Detection232
Calibration Clock Output233
Alarm Output233
RTC Power Saving Mode Management234
RTC Interrupts234
Table 15-1. RTC Power Saving Mode Management234
Table 15-2. RTC Interrupts Control234
Register Definition235
Time Register (RTC_TIME)235
Date Register (RTC_DATE)235
Control Register (RTC_CTL)236
Status Register (RTC_STAT)238
Prescaler Register (RTC_PSC)240
Alarm 0 Time and Date Register (RTC_ALRM0TD)240
Write Protection Key Register (RTC_WPK)242
Sub Second Register (RTC_SS)242
Shift Function Control Register (RTC_SHIFTCTL)242
Time of Time Stamp Register (RTC_TTS)243
Date of Time Stamp Register (RTC_DTS)244
Sub Second of Time Stamp Register (RTC_SSTS)244
High Resolution Frequency Compensation Register (RTC_HRFC)245
Tamper Register (RTC_TAMP)246
Alarm 0 Sub Second Register (RTC_ALRM0SS)248
Backup Registers (Rtc_Bkpx) (X = 0249
Timer (Timerx)251
Table 16-1. Timers (Timerx) Are Devided into Six Sorts251
Advanced Timer (Timerx ,X=0)252
Overview252
Characteristics252
Block Diagram253
Figure 16-1. Advanced Timer Block Diagram253
Function Overview254
Figure 16-2. Timing Chart of Internal Clock Divided by 1254
Figure 16-3. Timing Chart of PSC Value Change from 0 to 2255
Figure 16-4. Timing Chart of up Counting Mode, PSC=0/2256
Figure 16-5. Timing Chart of up Counting Mode, Change Timerx_Car on the Go257
Figure 16-6. Timing Chart of down Counting Mode, PSC=0/2258
Figure 16-7. Timing Chart of down Counting Mode, Change Timerx_Car on the Go258
Figure 16-8. Timing Chart of Center-Aligned Counting Mode260
Figure 16-9. Repetition Counter Timing Chart of Center-Aligned Counting Mode261
Figure 16-10. Repetition Counter Timing Chart of up Counting Mode261
Figure 16-11. Repetition Counter Timing Chart of down Counting Mode262
Figure 16-12. Channel Input Capture Principle263
Figure 16-13. Output-Compare under Three Modes265
Figure 16-14. EAPWM Timechart266
Figure 16-15. CAPWM Timechart266
Table 16-2. Complementary Outputs Controlled by Parameters267
Figure 16-16. Complementary Output with Dead-Time Insertion269
Figure 16-17. Output Behavior in Response to a Break(the Break High Active)270
Table 16-3. Counting Direction in Different Quadrature Decoder Mode270
Figure 16-18. Counter Behavior with CI0FE0 Polarity Non-Inverted in Mode 2271
Figure 16-19. Counter Behavior with CI0FE0 Polarity Inverted in Mode 2271
Figure 16-20. Hall Sensor Is Used to BLDC Motor271
Figure 16-21. Hall Sensor Timing between Two Timers273
Table 16-4. Slave Mode Example Table273
Figure 16-22. Restart Mode274
Figure 16-23. Pause Mode274
Figure 16-24. Event Mode275
Figure 16-25. Single Pulse Mode Timerx_Chxcv = 4 Timerx_Car=99275
Figure 16-26. TIMER0 Master/Slave Mode Timer Example276
Figure 16-67. Single Pulse Mode Timerx_Chxcv = 4 Timerx_Car=99276
Figure 16-27. Triggering TIMER0 with Enable Signal of TIMER1277
Figure 16-28. Triggering TIMER0 and TIMER1 with Timer1'S CI0 Input278
Register Definition280
General Level0 Timer (Timerx, X=1, 2)307
Overview307
Characteristics307
Block Diagram308
Figure 16-29. General Level 0 Timer Block Diagram308
Function Overview309
Figure 16-30. Timing Chart of Internal Clock Divided by 1309
Figure 16-31. Timing Chart of PSC Value Change from 0 to 2310
Figure 16-32. Timing Chart of up Counting Mode, PSC=0/2311
Figure 16-33. Timing Chart of up Counting Mode, Change Timerx_Car on the Go312
Figure 16-34. Timing Chart of down Counting Mode, PSC=0/2312
Figure 16-35. Timing Chart of down Counting Mode, Change Timerx_Car on the Go313
Figure 16-36. Center-Aligned Counter Timechart314
Figure 16-37. Channels Input Capture Principle316
Figure 16-38. Output-Compare under Three Modes318
Figure 16-39. EAPWM Timechart318
Figure 16-40. CAPWM Timechart318
Table 16-5. Examples of Slave Mode320
Figure 16-41. Restart Mode321
Figure 16-42. Pause Mode321
Figure 16-43. Event Mode321
Figure 16-65. Pause Mode321
Figure 16-66. Event Mode321
Figure 16-44. Single Pulse Mode Timerx_Chxcv = 4 Timerx_Car=99322
Table 16-6. Timerx(X=1,2) Interconnection323
Register Definition324
General Level2 Timer (Timerx, X=13)349
Overview349
Characteristics349
Figure 16-45. General Level2 Timer Block Diagram349
Figure 16-46. Timing Chart of Internal Clock Divided by 1350
Figure 16-47. Timing Chart of PSC Value Change from 0 to 2351
Figure 16-48. Timing Chart of up Counting Mode, PSC=0/2352
Figure 16-49. Timing Chart of up Counting Mode, Change Timerx_Car on the Go352
Figure 16-50. Channel Input Capture Principle353
Figure 16-51. Output-Compare under Three Modes355
Figure 16-52. PWM Mode Timechart355
Figure 16-53. General Level3 Timer Block Diagram368
Figure 16-54. Timing Chart of Internal Clock Divided by 1369
Figure 16-55. Timing Chart of PSC Value Change from 0 to 2370
Figure 16-56. Timing Chart of up Counting Mode, PSC=0/2371
Figure 16-57. Timing Chart of up Counting Mode, Change Timerx_Car on the Go372
Figure 16-58. Repetition Counter Timing Chart of up Counting Mode373
Figure 16-59. Channel Input Capture Principle374
Figure 16-60. Output-Compare under Three Modes376
Figure 16-61. PWM Mode Timechart376
Table 16-7. Complementary Outputs Controlled by Parameters378
Figure 16-62. Complementary Output with Dead-Time Insertion379
Figure 16-63. Output Behavior in Response to a Break(the Break High Active)380
Figure 16-64. Restart Mode381
Table 16-8. Slave Mode Example Table381
Table 16-9. Timerx(X=14) Interconnection383
Figure 16-68. General Level4 Timer Block Diagram406
Figure 16-69. Timing Chart of Internal Clock Divided by 1407
Figure 16-70. Timing Chart of PSC Value Change from 0 to 2408
Figure 16-71. Timing Chart of up Counting Mode, PSC=0/2409
Figure 16-72. Timing Chart of up Counting Mode, Change Timerx_Car on the Go410
Figure 16-73. Repetition Counter Timing Chart of up Counting Mode411
Figure 16-74. Channel Input Capture Principle412
Figure 16-75. Output-Compare under Three Modes414
Figure 16-76. PWM Mode Timechart414
Table 16-10. Complementary Outputs Controlled by Parameters416
Figure 16-77. Complementary Output with Dead-Time Insertion417
Figure 16-78. Output Behavior in Response to a Break (the Break High Active)418
Figure 16-79. Single Pulse Mode Timerx_Chxcv = 0X04 Timerx_Car=0X60419
Figure 16-80. Basic Timer Block Diagram437
Figure 16-81. Timing Chart of Internal Clock Divided by 1438
Figure 16-82. Timing Chart of PSC Value Change from 0 to 2439
Figure 16-83. Timing Chart of up Counting Mode, PSC=0/2440
Figure 16-84. Timing Chart of up Counting Mode, Change Timerx_Car on the Go440
Figure 17-1. IFRP Output Timechart 1447
Figure 17-2. IFRP Output Timechart 2448
Figure 17-3. IFRP Output Timechart 3448
Figure 18-1. USART Module Block Diagram451
Table 18-1. Description of USART Important Pins451
Figure 18-2. USART Character Frame (8 Bits Data and 1 Stop Bit)452
Table 18-2. Configuration of Stop Bits452
Figure 18-3. USART Transmit Procedure454
Figure 18-4. Oversampling Method of a Receive Frame Bit (OSB=0)455
Figure 18-5. Configuration Step When Using DMA for USART Transmission456
Figure 18-6. Configuration Step When Using DMA for USART Reception457
Figure 18-7. Hardware Flow Control between Two Usarts457
Figure 18-8. Hardware Flow Control458
Figure 18-9. Break Frame Occurs During Idle State459
Figure 18-10. Break Frame Occurs During a Frame460
Figure 18-11. Example of USART in Synchronous Mode460
Figure 18-12. 8-Bit Format USART Synchronous Waveform (CLEN=1)461
Figure 18-13. Irda SIR ENDEC Module461
Figure 18-14. Irda Data Modulation462
Figure 18-15. ISO7816-3 Frame Format463
Figure 18-16. USART Receive FIFO Structure465
Table 18-3. USART Interrupt Requests466
Figure 18-17. USART Interrupt Mapping Diagram467
Figure 19-1. I2C Module Block Diagram486
Table 19-1. Definition of I2C-Bus Terminology (Refer to the I2C Specification of Philips Semiconductors)487
Figure 19-2. Data Validation488
Figure 19-3. START and STOP Signal488
Figure 19-4. Clock Synchronization489
Figure 19-5. SDA Line Arbitration489
Figure 19-6. I2C Communication Flow with 7-Bit Address490
Figure 19-7. I2C Communication Flow with 10-Bit Address (Master Transmit)490
Figure 19-8. I2C Communication Flow with 10-Bit Address (Master Receive)490
Figure 19-9. Programming Model for Slave Transmitting (10-Bit Address Mode)492
Figure 19-10. Programming Model for Slave Receiving (10-Bit Address Mode)493
Figure 19-11. Programming Model for Master Transmitting (10-Bit Address Mode)495
Figure 19-12. Programming Model for Master Receiving Using Solution a (10-Bit Address Mode)497
Figure 19-13. Programming Model for Master Receiving Mode Using Solution B (10-Bit Address Mode)499
Table 19-2. Event Status Flags502
Table 19-3. Error Flags502
Figure 20-1. Block Diagram of SPI516
Table 20-1. SPI Signal Description516
Figure 20-2. SPI Timing Diagram in Normal Mode517
Table 20-2. Quad-SPI Signal Description517
Figure 20-3. SPI Timing Diagram in Quad-SPI Mode (CKPL=1, CKPH=1, LF=0)518
Table 20-3. NSS Function in Slave Mode518
Table 20-4. NSS Function in Master Mode519
Table 20-5. SPI Operating Modes519
Figure 20-4. a Typical Full-Duplex Connection520
Figure 20-5. a Typical Simplex Connection (Master: Receive, Slave: Transmit)521
Figure 20-6. a Typical Simplex Connection (Master: Transmit Only, Slave: Receive)521
Figure 20-7. a Typical Bidirectional Connection521
Figure 20-8. Timing Diagram of TI Master Mode with Discontinuous Transfer523
Figure 20-9. Timing Diagram of TI Master Mode with Continuous Transfer523
Figure 20-10. Timing Diagram of TI Slave Mode524
Figure 20-11. Timing Diagram of NSS Pulse with Continuous Transmit525
Figure 20-12. Timing Diagram of Write Operation in Quad-SPI Mode526
Figure 20-13. Timing Diagram of Read Operation in Quad-SPI Mode527
Figure 20-14. Block Diagram of I2S530
Table 20-6. SPI Interrupt Requests530
Figure 20-15. I2S Phillips Standard Timing Diagram (DTLEN=00, CHLEN=0, CKPL=0)531
Figure 20-16. I2S Phillips Standard Timing Diagram (DTLEN=00, CHLEN=0, CKPL=1)532
Figure 20-17. I2S Phillips Standard Timing Diagram (DTLEN=10, CHLEN=1, CKPL=0)532
Figure 20-18. I2S Phillips Standard Timing Diagram (DTLEN=10, CHLEN=1, CKPL=1)532
Figure 20-19. I2S Phillips Standard Timing Diagram (DTLEN=01, CHLEN=1, CKPL=0)532
Figure 20-20. I2S Phillips Standard Timing Diagram (DTLEN=01, CHLEN=1, CKPL=1)532
Figure 20-21. I2S Phillips Standard Timing Diagram (DTLEN=00, CHLEN=1, CKPL=0)533
Figure 20-22. I2S Phillips Standard Timing Diagram (DTLEN=00, CHLEN=1, CKPL=1)533
Figure 20-23. MSB Justified Standard Timing Diagram (DTLEN=00, CHLEN=0, CKPL=0)533
Figure 20-24. MSB Justified Standard Timing Diagram (DTLEN=00, CHLEN=0, CKPL=1)533
Figure 20-25. MSB Justified Standard Timing Diagram (DTLEN=10, CHLEN=1, CKPL=0)534
Figure 20-26. MSB Justified Standard Timing Diagram (DTLEN=10, CHLEN=1, CKPL=1)534
Figure 20-27. MSB Justified Standard Timing Diagram (DTLEN=01, CHLEN=1, CKPL=0)534
Figure 20-28. MSB Justified Standard Timing Diagram (DTLEN=01, CHLEN=1, CKPL=1)534
Figure 20-29. MSB Justified Standard Timing Diagram (DTLEN=00, CHLEN=1, CKPL=0)534
Figure 20-30. MSB Justified Standard Timing Diagram (DTLEN=00, CHLEN=1, CKPL=1)534
Figure 20-31. LSB Justified Standard Timing Diagram (DTLEN=01, CHLEN=1, CKPL=0)535
Figure 20-32. LSB Justified Standard Timing Diagram (DTLEN=01, CHLEN=1, CKPL=1)535
Figure 20-33. LSB Justified Standard Timing Diagram (DTLEN=00, CHLEN=1, CKPL=0)535
Figure 20-34. LSB Justified Standard Timing Diagram (DTLEN=00, CHLEN=1, CKPL=1)535
Figure 20-35. PCM Standard Short Frame Synchronization Mode Timing Diagram (DTLEN=00, CHLEN=0, CKPL=0)536
Figure 20-36. PCM Standard Short Frame Synchronization Mode Timing Diagram537
Figure 20-37. PCM Standard Short Frame Synchronization Mode Timing Diagram537
Figure 20-38. PCM Standard Short Frame Synchronization Mode Timing Diagram537
Figure 20-39. PCM Standard Short Frame Synchronization Mode Timing Diagram (DTLEN=01, CHLEN=1, CKPL=0)537
Figure20-40. PCM Standard Short Frame Synchronization Mode Timing Diagram (DTLEN=01, CHLEN=1, CKPL=1)537
Figure 20-41. PCM Standard Short Frame Synchronization Mode Timing Diagram (DTLEN=00, CHLEN=1, CKPL=0)537
Figure 20-42. PCM Standard Short Frame Synchronization Mode Timing Diagram (DTLEN=00, CHLEN=1, CKPL=1)537
Figure 20-43. PCM Standard Long Frame Synchronization Mode Timing Diagram537
Figure20-44. PCM Standard Long Frame Synchronization Mode Timing Diagram537
Figure 20-45. PCM Standard Long Frame Synchronization Mode Timing Diagram (DTLEN=10, CHLEN=1, CKPL=0)538
Figure 20-46. PCM Standard Long Frame Synchronization Mode Timing Diagram (DTLEN=10, CHLEN=1, CKPL=1)538
Figure 20-47. PCM Standard Long Frame Synchronization Mode Timing Diagram (DTLEN=01, CHLEN=1, CKPL=0)538
Figure 20-48. PCM Standard Long Frame Synchronization Mode Timing Diagram (DTLEN=01, CHLEN=1, CKPL=1)538
Figure 20-49. PCM Standard Long Frame Synchronization Mode Timing Diagram (DTLEN=00, CHLEN=1, CKPL=0)539
Figure 20-50. PCM Standard Long Frame Synchronization Mode Timing Diagram (DTLEN=00, CHLEN=1, CKPL=1)539
Figure 20-51. Block Diagram of I2S Clock Generator539
Table 20-7. I2S Bitrate Calculation Formulas539
Figure 20-52. I2S Initialization Sequence540
Table 20-8. Audio Sampling Frequency Calculation Formulas540
Table 20-9. Direction of I2S Interface Signals for each Operation Mode540
Figure 20-53. I2S Master Reception Disabling Sequence543
Table 20-10. I2S Interrupt545
Figure 21-1. HDMI-CEC Controller Block Diagram558
Figure 21-2. Start Bit559
Figure 21-3. Valid Data Bit559
Table 21-1. Data Bit Timing Parameter Table559
Figure 21-4. Signal Free Time560
Figure 21-5. Error Bit Period561
Figure 21-6. Bit Period Long Error562
Figure 21-7. Transmission Error Detection563
Table 21-2. Error Handling Timing Parameter Table563
Table 21-3. TERR Timing Parameter Table564
Figure 22-1. Block Diagram of TSI Module574
Figure 22-2. Block Diagram of Sample Pin and Channel Pin575
Table 22-1. Pin and Analog Switch State in a Charge-Transfer Sequence576
Figure 22-3. Voltage of a Sample Pin During Charge-Transfer Sequence577
Figure 22-4. FSM Flow of a Charge-Transfer Sequence578
Table 22-2. Duration Time of Extend Charge State in each Cycle579
Table 22-3. Extend Charge Deviation Base on HCLK Period580
Table 22-4. TSI Errors and Flags581
Table 22-5. TSI Pins581
Figure 23-1. USBFS Block Diagram593
Table 23-1. USBFS Signal Description593
Figure 23-2. Connection with Host or Device Mode594
Figure 23-3. Connection with OTG Mode595
Figure 23-4. State Transition Diagram of Host Port595
Figure 23-5. HOST Mode FIFO Space in SRAM600
Figure 23-6. Host Mode FIFO Access Register Map600
Figure 23-7. Device Mode FIFO Space in SRAM601
Figure 23-8. Device Mode FIFO Access Register Map601
Table 23-2. USBFS Global Interrupt606
Table 24-1. Revision History666

Brand	GigaDevice Semiconductor
Model	GD32F3 0 Series
Category	Microcontrollers
Language	English

GigaDevice Semiconductor GD32F3 0 Series - User Manual

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GigaDevice Semiconductor GD32F3 0 Series Specifications

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