GigaDevice Semiconductor GD32F3x0 - I; O Compensation Cell; Table 1-3. Boot Modes

GD32F3x0 User Manual
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Table 1-3. Boot modes
Selected boot source
Boot mode selection pins
Boot1
Boot0
Main Flash Memory
x
0
System Memory
0
1
On-chip SRAM
1
1
1. The Boot1 value is the opposite of the BOOT1_n value.
After power-on sequence or a system reset, the Arm
®
Cortex
®
-M4 processor fetches the
top-of-stack value from address 0x0000 0000 and the base address of boot code from
0x0000 0004 in sequence. Then, it starts executing code from the base address of boot
code.
According to the selected boot source, either the main flash memory (original memory space
beginning at 0x0800 0000) or the system memory (original memory space beginning at
0x1FFF EC00) is aliased in the boot memory space which begins at the address 0x0000
0000. When the on-chip SRAM whose memory space is beginning at 0x2000 0000 is
selected as the boot source, in the application initialization code, you have to relocate the
vector table in SRAM using the NVIC exception table and offset register.
The embedded boot loader is located in the System memory, which is used to reprogram the
Flash memory. The boot loader can be activated through one of the following serial
interfaces: USART0 or USART1.
1.5. I / O compensation cell
By default, the I / O compensation cell is not used. However, when the I / O port output
speed is more than 50MHz, it is recommended to use the compensation cell for slew rate
control to reduce the I / O noise on power supply.
When the compensation cell is enabled, a complete flag CPS_RDY in the register
SYSCFG_CPSCTL is set to indicate that the compensation cell is ready and can be used.