GD32F3x0 User Manual
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2.3.6. Main flash programming
The FMC provides a 32-bit word / 16-bit half word / bit programming function which is used to
modify the main flash memory contents. The following steps show the word programming
operation register access sequence.
1. Unlock the FMC_CTL register if necessary.
2. Check the BUSY bit in FMC_STAT register to confirm that no flash memory operation is
in progress (BUSY equal to 0). Otherwise, wait until the operation has been finished.
3. Write the word program command into the PG bit in FMC_CTL register.
4. A 32-bit word/16-bit half word write at desired address by DBUS.
5. Wait until all the operations have been completed by checking the value of the BUSY bit
in FMC_STAT register.
6. Read and verify the flash memory by using a DBUS access if necessary.
When the operation is executed successfully, an interrupt will be triggered by FMC if the
ENDIE bit in the FMC_CTL register is set, and the ENDF in FMC_STAT register is set. It is
notable that checking whether the target address content is 0xFF before the word/half word
programming operation. If he target address content is not 0xFF, PGERR bit will set when
programming the address except that program content is 0x0. Additionally, the program
operation would be ignored on protected pages. A flash operation error interrupt would be
triggered by the FMC if the ERRIE bit in the FMC_CTL register is set. The software can
check the PGERR and WPERR bit in the FMC_STAT register to detect the interrupt
condition in the interrupt handler. The end of this operation is indicated by the ENDF bit in
the FMC_STAT register. The following figure displays the word programming operation flow.
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