GD32F3x0 User Manual
47
2.3.8. Option byte programming
The FMC provides a 16-bit half word programming function which is used for modifying the
option byte block contents. The following steps show the programming operation sequence.
1. Unlock the FMC_CTL register if necessary.
2. Unlock the OBWEN bit in FMC_CTL register if necessary.
3. Check the BUSY bit in FMC_STAT register to confirm that no flash memory operation is
in progress (BUSY equal to 0). Otherwise, wait until the operation has been finished.
4. Write the program command into the OBPG bit in FMC_CTL register.
5. 16-bit half word write at desired address by DBUS.
6. Wait until all the operations have been completed by checking the value of the BUSY bit
in FMC_STAT register.
7. Read and verify the flash memory by using a DBUS access if necessary.
When the operation is executed successfully, an interrupt will be triggered by FMC if the
ENDIE bit in the FMC_CTL register is set, and the ENDF in FMC_STAT register is set. It is
notable that checking whether the target address content is 0xFF before the word/half word
programming operation. If the target address content is not 0xFF, PGERR bit will set when
program the target address. The end of this operation is indicated by the ENDF bit in the
FMC_STAT register.
2.3.9. Option byte description
The option bytes block of flash memory reloaded to FMC_OBSTAT and FMC_WP registers
after each system reset or OBRLD bit set in FMC_CTL register, and then the option bytes
take effect. The option complement bytes are the opposite of option bytes. When option
bytes reload, if the option complement bytes and option bytes does not match, the OBERR
bit in FMC_OBSTAT register is set, and the option byte is set to 0xFF. The following table is
the detail of option bytes.
Table 2-2. Option byte
option byte which user defined
[7]: Reserved
[6]: SRAM_PARITY_CHECK
0: Enable sram parity check
1: Disable sram parity check
[5]: VDDA_VISOR
0: Disable V
DDA
monitor, factory setting value, should be
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