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GigaDevice Semiconductor GD32F3x0 - Figure 16-12. Channel Input Capture Principle

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GD32F3x0 User Manual
262
Figure 16-12. Channel input capture principle
CI0
Synchronizer
D
presclare
Capture
Register
CH0VAL
Clock
Processer
Counter
TIMER_CK
Q
Filter
D Q D Q
Edge Detector
CI1FE0
ITS
CH0MS
CH0IF
CH0IE
CH0_CC_I
TIMERx_CC_INT
Capture INT From Other Channal
CH0CAPPSC
Edge selector
&inverter
Based on
CH0P&CH0NP
CI0FE0
Rising/Falling
ITI0
ITI3
ITI1
ITI2
CI0FED
Rising&Falling
IS0
CI0FED
One of channels’ input signals (CIx) can be chosen from the TIMERx_CHx signal or the
Excusive-OR function of the TIMERx_CH0, TIMERx_CH1 and TIMERx_CH2 signals. First,
the channel input signal (CIx) is synchronized to TIMER_CK domain, and then sampled by a
digital filter to generate a filtered input signal. Then through the edge detector, the rising and
falling edge are detected. You can select one of them by CHxP. One more selector is for the
other channel and trig, controlled by CHxMS. The IC_prescaler make several the input
events generate one effective capture event. On the capture event, CHxVAL will restore the
value of Counter.
So, the process can be divided to several steps as below:
Step1: Filter configuration. (CHxCAPFLT in TIMERx_CHCTL0)
Based on the input signal and requested signal quality, configure compatible
CHxCAPFLT.
Step2: Edge selection. (CHxP/CHxNP in TIMERx_CHCTL2)
Rising or falling edge, choose one by CHxP/CHxNP.
Step3: Capture source selection. (CHxMS in TIMERx_CHCTL0)
As soon as you select one input capture source by CHxMS, you have set the channel
to input mode (CHxMS! = 0x0) and TIMERx_CHxCV cannot be written any more.
Step4: Interrupt enable. (CHxIE and CHxDEN in TIMERx_DMAINTEN)
Enable the related interrupt to get the interrupt and DMA request.
Step5: Capture enables. (CHxEN in TIMERx_CHCTL2)

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