GigaDevice Semiconductor GD32F3x0 - Figure 20-3. SPI Timing Diagram in Quad-SPI Mode (CKPL=1, CKPH=1, LF=0); Table 20-3. NSS Function in Slave Mode

GD32F3x0 User Manual
515
Figure 20-3. SPI timing diagram in Quad-SPI mode (CKPL=1, CKPH=1, LF=0)
MOSI
MISO
NSS
D0[4] D0[0]
D1[4]
D1[0]
D0[5] D0[1]
D1[5]
D1[1]
sample
IO2
IO3
D0[6] D0[2]
D1[6]
D1[2]
D0[7] D0[3]
D1[7]
D1[3]
SCK
In normal mode, the length of data is configured by the FF16 bit in the SPI_CTL0 register.
Data length is 16 bits if FF16=1, otherwise is 8 bits. The data frame length is fixed to 8 bits in
Quad-SPI mode.
Data order is configured by LF bit in SPI_CTL0 register, and SPI will send the LSB first if
LF=1, or the MSB if LF=0. The data order is fixed to MSB first in TI mode.
20.3.4. NSS function
Slave mode
When slave mode is configured (MSTMOD=0), SPI gets NSS level from NSS pin in
hardware NSS mode (SWNSSEN = 0) or from SWNSS bit in software NSS mode
(SWNSSEN = 1) and transmits/receives data only when NSS level is low. In software NSS
mode, NSS pin is not used.
Table 20-3. NSS function in slave mode
Mode
Register configuration
Description
Slave hardware NSS mode
MSTMOD = 0
SWNSSEN = 0
SPI slave gets NSS level from NSS pin.
Slave software NSS mode
MSTMOD = 0
SWNSSEN = 1
SPI slave NSS level is determined by
the SWNSS bit.
SWNSS = 0: NSS level is low
SWNSS = 1: NSS level is high
Master mode
In master mode (MSTMOD=1) if the application uses multi-master connection, NSS can be
configured to hardware input mode (SWNSSEN=0, NSSDRV=0) or software mode
(SWNSSEN=1). Then, once the NSS pin (in hardware NSS mode) or the SWNSS bit (in